JPS61118854A - Store buffer control system - Google Patents

Abstract

PURPOSE:To avoid the increase of hardware quantity by providing a 2N-byte store buffer to store the store data of 2N bytes covering the 2N-byte boundary by two N-byte store operations. CONSTITUTION: The store data 9 are arrayed by an alignment circuit 4 and stored to a data register 1A. While a store address 11 is stored to a store address register 3A and also applied to a byte mark generating circuit 5 together with the store length 10. The produced byte marks are stored to a byte mark register 2A. A store control circuit 8 refers to the stored byte mark and store address transfers the N-byte data which does not cover the N-byte boundary to a main memory with a single N-byte store operation together with the 2N-byte data which does not cover the 2N-byte boundary with a single 2N-byte store operation. When the 2N-byte data covers the 2N-byte boundary, the two times of N-byte store operations are indicated for transfer of the data to the main memory.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a method for efficiently storing data temporarily stored in the store buffer device provided between a central processing unit and a main storage device. Store buffer control method for transferring to main memory In recent data processing devices, when executing a series of programs, attention is paid to the locality of the address distribution of the program, and the capacity is small, but
It is well known that instruction processing is speeded up by providing a high-speed buffer memory in the main storage device.

When the buffer memory is used in a store-through type, a store buffer register is provided in the central processing unit to alleviate the concentration of store accesses to the main memory, so that store access from the central processing unit to the main memory can be reduced. There are known methods for shortening the apparent access time for store access.

That is, it attempts to improve the processing power of the central processing unit by equalizing the store accesses to the main memory.

In this case, on the main memory side, from an economical perspective,
Generally, the basic access unit is, for example, 8 bytes, and the central processing unit and the main memory are also connected by an 8-byte wide data bus. Also, since the transfer time between the central processing unit and the main memory is longer than the processing time in the central processing unit, it takes a long time for the central processing unit to complete the process after the response to the store request is returned and before sending the next store request. The time required is the equivalent of two performance cycles.

Therefore, these 8 bytes are the basic access vehicles.

In general, when the above store buffer device is provided for a main memory device whose basic access unit is N bytes, a store buffer device suitable for the main memory device whose basic access unit is N bytes is provided. A control method is required.

[Conventional technology]

For example, Figures 5 and 6 schematically show the configuration of a conventional store buffer device provided for a main memory (not shown, the same applies hereinafter) whose basic access unit is 8 bytes. show. Fig. 5 shows an example in which the data width of the data register in the store buffer device is set to 8 bytes, for example, and Fig. 6 shows an example in which the data width of the data register is set to 2x8 = 16 bytes. The same symbols in both figures indicate functionally the same objects.

In any of the above methods, the store buffer device includes a data register IA that temporarily holds store data from a central processing unit (not shown, the same applies hereinafter), and a data register IA that indicates the validity of each byte of the data register IA. A plurality of sets (four sets in this figure) of store buffers each having one height mark register 2A in which a flag is placed are provided.

In this figure, the align circuit (^L) 4 stores the store data sent from the central processing unit into the main memory 8.
In order to protect byte boundaries (that is, boundaries for using 8 bytes as a basic access unit), it has a function of aligning using the store address sent from the central processing unit.

Furthermore, the byte mark generation circuit (BM) 5 has a function of generating a byte mark corresponding to the store data based on the store address and store length sent from the central processing unit.

When the word length of data register IA in FIG. 5 is 8 bytes, store requests within 8 bytes that do not cross 8-byte boundaries in the main memory are stored in the 1m store buffer indicated by inpointer 6, When transfer to the main memory becomes possible (once every two cycles when the main memory is not busy), a store request is sent to the main memory and the data register LA , the byte mark register 2A, and the store address register 3A, one set of contents indicated by the out pointer 7 is selected by the selectors IC, 2C, and 3B, respectively, and the data transfer bus 12. Byte mark transfer bus13. It was transferred to the main storage device via the store address transfer bus 15.

FIG. 6 shows an example in which a data register IA with a width of 16 heights and a corresponding byte mark register 2A are provided in order to improve the problems described later that occur in the example of FIG.

Store requests from the central processing unit include those with a data width of 8 bytes or less and those with a data width of 16 bytes, but in this example, 16-height data within a 16-byte boundary is
two store buffers (i.e., data register l^,
It can be stored in the byte mark register 2A), and data of 8 bytes or less that crosses an 8-byte boundary in main memory can also be stored in one store buffer. be.

[Problem that the invention seeks to solve]

Among the conventional methods described above, in the example shown in FIG. 5, store data within 8 bytes that does not cross the 8-byte boundary of the main memory can only be stored in the data register 1^.
In the store buffer device, when a large number of store requests are sent from the central processing unit in a short period of time, there is a problem that the free store buffer quickly runs out and the central processing unit has to interrupt processing of subsequent instructions. arise.

Next, in the example of FIG. 6, a store request from the central processing unit on the store puffer node, i.e., a store request for data of 6 heights or less within a 16-byte boundary of the main memory, or a single 8-byte boundary. The method is to send a store request for data of 8 bytes or more that spans F to the eugenic storage device. It is not possible to hold store data in one store buffer, and there is a data transfer bus 12.2 that corresponds to 16-byte wide data between the store buffer device and the main storage device. In addition, a 16-bit wide byte mark transfer path is required, resulting in an increase in the amount of hardware.

In view of the above-mentioned drawbacks of the conventional art, the present invention has been proposed to process a store request from a central processing unit stored in, for example, a 16-byte wide data register and a 16-bit wide byte mark register, by checking the contents of the byte mark register and the store address register. This is done by using an 8-byte wide data transfer bus and an 8-bit wide byte mark transfer path, without increasing the amount of hardware between the store buffer device and the main memory device, and improving the data transfer efficiency between both devices. The purpose is to provide a method for improving the

[Means for solving problems]

This purpose is controlled by the contents of the byte mark register and the store address register, and for example, if the store data is within 8 bytes and does not span an 8-byte boundary, the purpose is to perform one 8-byte store operation, and to If the store data is within 16 bytes that does not span a boundary, it is performed as one 16-byte store operation, and if the store data is more than 16 bytes that spans a 16-height boundary, it is performed as two 8-byte store operations. This is achieved by the store buffer control method of the present invention, which includes means for storing data and transferring the contents of the data register, byte mark register, and store address register to the main memory in response to a store operation generated by each means. Ru.

[Effect]

That is, according to the present invention, a store request from the central processing unit stored in, for example, a 16-height data register and a 16-hint width byte mark register is determined based on the contents of the byte mark register and the store address register. and one 8-byte store operation, 1
An 8-byte wide data transfer bus provided between the store buffer device and the main memory device, and an 8-bit wide data transfer bus for one 16-byte store operation or two 8-byte store operations. This is a byte mark transfer path that can be used to store data of 16 bytes or less that straddles one of the boundaries, which is an 8-byte boundary and a 16-byte boundary, which is not seen in the conventional example. The data transfer efficiency between the store buffer device and the main storage device can be improved without increasing the amount of hardware between the store buffer device and the main storage device. There are effects that can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram schematically showing an embodiment of the present invention,
FIG. 2 is a diagram showing an example of a store request from a central processing unit stored in a store buffer by implementing the present invention.
FIG. 3 is a diagram showing a store operation generation circuit, which is the main focus of the present invention, and FIG.
FIG. 3 is a diagram showing the operation when performing a store operation using a time chart I. FIG. 1, the same symbols as in FIGS. 5 and 6 indicate the same objects, and the selector 2D, store control circuit 8, and adder 16 are functional blocks necessary to implement the present invention.

The present store buffer device shown in FIG. 1 is also equipped with four sets of store buffers, and each store buffer is
For example, a 16-byte wide data register IA and a 16-byte byte mark register 2A.

It is equipped with a store address register 3A.

Now, when there is a store request from the central processing unit, 8-byte wide store data is sent from the store data bus 9.

From store length pass 10, this = Pig store data,
A store length indicating the length of bytes to be actually stored in the main memory, and an address on the main memory where the store data is to be stored are sent from the store address bus 11.

In this store buffer device, in view of the fact that the address space in the main memory is on an 8-byte boundary, the align circuit (
AL) Align the store data using 4.

Also, based on the above store address and store length,
A byte mark generation circuit (BM) 5 is used to generate byte marks corresponding to the aligned store data.

The above store data and byte mark are stored in the data length LA of the store buffer indicated by the in-pointer 6 and the byte mark register 2A, respectively, and the lower 3 bits of the store address from the store address bus 11 are set to O”. (These lower 3 bits do not actually need to be held in the store address bus register 3A, nor do they need to be transferred to the main storage device) are stored in the store address register 3A.

Next, a comparison circuit (not shown) compares the store address sent from the store address bus 11 with the value of the store address register currently indicated by the inpointer 6, and determines whether the store address has already been stored in the store buffer. It is determined whether the current store request can be merged with the existing store request, and if the current store request can be merged, the align circuit (AL)
4. and through the bite mark generation circuit (BM) 5,
The above data register IA and byte mark register 2
Merged with A.

For example, if the store address of the current store data is a contiguous address to the store data already stored in the data register 16, and the total amount of data does not exceed the next 16-byte boundary, the same data register 1 8 (specifically, performing a partial store in the data register IA).

FIG. 2 shows an example of store request data from the central processing unit stored in a set of store buffers using the above method.

In this figure, the store address is shown in bits, bits 28 to 31, and the store data is shown in the align circuit (A) 4.
Valid bytes obtained by aligning the corresponding bytes are shown with diagonal lines, and the byte marks are shown as 1° when the corresponding byte is valid, and as 0 when the corresponding byte is invalid.

The examples in ■ and ■ are for store data of 8 bytes or less that does not span an 8-byte boundary or a 16-height boundary, and the example in ■ is for store data that is within 16 bytes that does not span a 16-byte boundary. In this case, ■ indicates the case of store data within 16 bytes that straddles a 16-height boundary.

Store data from the central processing unit can all be applied to any of the examples ① to ② above.

For example, store data within 8 bytes that straddles an 8-byte boundary can be applied to the above-mentioned (2) or (2).

The store operation when storing such store data in the main memory by implementing the present invention is shown in FIG.
FIG. 3 with reference to FIG.

This will be explained with reference to FIG.

First, among the store requests from the central processing unit that have already been stored in the store buffer, the byte mark register 2 pano hits 8 to 15 .
&['The value of store address register 3A is selector 2
D, selected by 3B.

The store control circuit 8 controls the byte mark bits 8 to 15.
．． and store address bits 28 are used to select the store operation of the present invention by the logic circuit shown in FIG.

In a) of this figure, when the OR circuit 81 is at logic °o°, that is, when byte mark bits 8 to 15 are all at °o', the NOT circuit 82
is turned on to instruct one 8-byte store operation.

This 3-byte store operation is selected when the store data is within 8 bytes and does not span an 8-byte boundary, and the examples of ■ and ■ in FIG. 2 correspond to this.

Generally, store data within 8 bytes that does not span an 8-byte boundary is aligned to the upper 8 bytes of the data register IA, so the above selection can be made.

In b), one of the byte mark focuses of the OR circuit 81 is “1” and the store address bit 28 is “0”.
At this time, the AND circuit 83 is turned on to instruct one 16-height store operation.

This operation is selected when the store data is less than 1 byte and does not straddle a 16-byte boundary, and corresponds to the example ◯ in FIG. 2.

C) turns on the AND circuit 83 and instructs two 8-byte store operations when any of the byte mark bits in the OR circuit 81 is 1 and the store address bit 28 is 1. .

This operation is selected when store data of 16 bytes or less spans a 16-byte boundary, and corresponds to the example ◯ in FIG. 2.

The main memory is configured to accept 8-byte store operations within 8-byte boundaries and 16-byte store operations within 16-byte boundaries, and both store operations complete in two cycles. do. For 8-byte operations, 2
It is necessary to store inter-cycle store data and byte marks in the main memory, and in the case of a 16-byte store operation, ■ the upper 8 bytes or 8 bits are stored in the 2nd cycle, and the lower 8 bytes or It is necessary to send bit store data and byte marks.

Furthermore, both store operations send out a command indicating the store address and the type of store operation for two cycles. In the case of a 16-byte store operation, an address on a 16-byte boundary is required as the store address.

The above-mentioned operations in the main memory are shown in FIG.
When applied to the store operation in C), the timing is shown in FIG.

First, in the case of a) one 8-byte store operation, selector IB and selector 2B select the upper 8 bytes of data register IA and byte mark register 2A.
The top eight hits are selected in each store buffer, and then data register 1^, byte mark register 2A, and store address register 38 of the store buffer indicated by out pointer 7 are selected by selectors IC, 2C, and 3B. , data transfer lotus 12, byte mark transfer lotus 13., respectively. The data is sent to the store address transfer bus 15 for two cycles. (See 21 to 23) At this time, the store operation command bus 14 has
The store control circuit 8 instructs the above-mentioned 8-byte store operation for two cycles. (Refer to 20) Next, in the case of one 16-byte store operation in b), in the first cycle, the upper 8 bytes of data register LA and the upper 8 pins of byte mark register 2A are
Selector IB and selector 2B select, and in the second cycle, the lower 8 bytes of data register IA and the lower 8 bits of byte mark register 2A are selected. In both cycles, the operations of selectors IC, 2C, and 3B are as described above. a)
The same is true for . (See 25 to 27) At this time, the store operation command bus 14 has 2
During the cycle, a 16-byte store operation is indicated. (Refer to 24) Next, in the case of the two 8-byte store operations in c), the upper 8 bytes of data register LA are used for the first two cycles.
The byte and the upper 8 bits of the byte mark register 2A are selected by selector IB and selector 2B, and for the following two cycles, the first 8 bits of the data register IA and the lower 8 bits of the byte mark register 2A are selected by the selector IB and selector 2B. The operation of selectors lc, 2c, and 3B is the same as in case a) for both two cycles (that is, for four cycles). However, in this case, since there are two 8-byte store operations, the value of the store address selected by selector 3B remains unchanged for the first two cycles.
During the following two cycles, the adder 16 adds 8 to that value and sends the value to the store address transfer bus 15. (See 29, 30, 31) At this time, the store operation command bus 14 has
In all four cycles, an 8-byte store operation is instructed. (Refer to 28) In this way, in the present invention, a store request to a main storage device of 16 bytes or less within a 16-byte boundary, or a store request to a main storage device of 16 bytes or less that straddles one 8-byte boundary, It has an 8-byte wide data transfer path and is characterized by efficient processing.

〔Effect of the invention〕

As described above in detail, the store buffer control method of the present invention uses a 16-byte wide data register and a 16-byte wide data register.
A store request from the central processing unit stored in the bit-wide bytemark register is sent to the bytemark register.
and the contents of the store address register, the store buffer device performs one 8-byte store operation, one 16-byte store operation, or two 8-byte store operations. This can be done using an 8-byte wide data transfer bus and an 8-byte wide byte mark transfer bus provided between the main memory and the main memory, which is not seen in conventional examples. It is possible to provide a means for transferring store data to the main storage device from a store buffer that can hold store data of 16 bytes or less spanning one of the boundaries that is an 8-byte boundary and a 16-byte boundary, and the store buffer This has the effect of improving data transfer efficiency between the devices and the main storage device without increasing the amount of hardware between the two devices.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of a store request from a central processing unit stored in a store buffer by implementing the present invention. FIG. 3 is a diagram showing an example of a store control circuit. FIG. 4 is a time chart showing the operation when performing a store operation by implementing the present invention. FIG. 5 is a diagram schematically showing an example of a conventional method. FIG. 6 is a diagram schematically showing another example of the conventional method. It is. In the drawing, IA is a data register. 28 is a byte mark register. 38 is a store address register. 1B, 2B, 3B, IG, 2G, 2D are selectors. 4 is an align circuit (AL). 5 is a bite mark generation circuit (IIM). 6 is in pointer 3 7 is out pointer. 8 is a store control circuit, and 9 is a store data bus. 10 is a store length bus. 11 is a store address bus. 12 is a data transfer path. 13 is a byte mark transfer bus. 14 is a store operation command bus. 15 is a store address transfer lotus. 16 is an adder. are shown respectively. Brown 1st qz Eyed tea 3 Prisoner tea 48 1i) lth 1113 pie > strike? ohalation b)
I M = a 14 Tsumaitost 7O to O ration 5gl

Claims (1)

[Claims] In a data processing device equipped with a main memory device whose basic access unit is N (where N is a positive integer) bytes,
A 2N byte wide data register, a byte mark register that holds a flag indicating the validity of each byte of data in the data register, and a store address register that indicates the address in main memory where the data in the data register is stored. A plurality of sets of store buffers are provided, and each store buffer receives a store request for a main memory of 2N bytes or less within the 2N byte boundary of the main memory, or one of the above N byte boundaries. In a store buffer device that can store a store request to the main memory of 2N bytes or less that spans, when storing to the main memory, it is controlled by the contents of the byte mark register and store address register, and does not span the N byte boundary. N
If the store data is within a byte, one N-byte store operation is performed, and if the store data is within 2N bytes and does not span a 2N byte boundary, one 2-byte store operation is performed.
2 if there is a means to perform an N-byte store operation and the store data is within 2N bytes that spans a 2N-byte boundary.
means for performing N byte store operations, and transferring the contents of the data register, byte mark register, and store address register to the main storage device in response to the store operation generated by each means. Store buffer control method.