JPH01150951A - Memory access method - Google Patents

Abstract

PURPOSE:To totally obtain only desired data at a high speed without especially giving attention to the address position, etc., of the tip and termination of the data by reading instructed successive data for a transferring number from the data on an address, which is instructed from a memory device, and transferring the successive data to a request source. CONSTITUTION:When the successive data on a memory device 3 are totally obtained, the request source (an operation control device) instructs a memory data request, the address of the head data of a data group and the data transferring number to a memory control device 2. The memory control device 2 reads transferring block data for the successive instructed data transferring number from the transferring block data to correspond to the head address, which is instructed from the request source, and transfers the data to the request source. Accordingly, the request source can totally obtain only the desired data at the high speed without giving attention to the address position, etc., of the tip and termination of the desired data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device, and more particularly to a data processing device including a request source, a memory control device, and a memory device.

(Prior Art) Conventionally, in this type of data processing device, when a request source such as an arithmetic and control unit wishes to obtain continuous data on a memory all at once, a block data transfer request (
Also called a block load request. ).

In this case, the request source sends a block load request to the memory control device along with the start address of the required memory data. The memory control device reads the accessed block data from the memory device, divides it into a plurality of sections, and transfers the block data in a plurality of times, starting with the transfer section data at the accessed address. For example, if one block of data is 64 bytes, as shown in Figure 2, this 64-byte block data is the data length determined by the data transfer width between the request source and the memory control device, in this case. Block data is divided into 8 bytes and transferred 8 times. Here, if a word number is added in the increasing address direction for every 8-byte data from the beginning of the block boundary as shown in FIG. 2, and the beginning address of the memory data requested by the request source indicates word number 4, The order in which the corresponding block data is transferred to the request source is word number 4 - word number 5 - word number 6 - word number 7.
- Word number 0 - Word number 1 - Word number 2 - Word number 3.

[Problem that the invention seeks to solve]

In the conventional data processing device described above, for example, the element data required by the arithmetic control unit that is the request source is stored in word number 4 from the middle of a block boundary to the middle of the next block boundary, as shown in FIG. If the data is consecutively arranged from word number 13 to word number 13, it is impossible to obtain the required data all at once by a block load request. That is, when a block load request is sent with an address for word number 4, in addition to the necessary element data from word number 4 to word number 7, unnecessary data from word number 0 to word number 3 is sent. will also be transferred. Furthermore, in order to obtain the remaining element data, if a block load request is sent with the address for word number 8, in addition to the element data from word number 8 to word number 13 that is needed, word number 14 and word number 15 are also transferred. This results in delays in processing for selecting necessary data and unnecessary data within the arithmetic and control unit that is the request source, and in request processing for reading and transferring unnecessary data from the memory device. Therefore, the request source had to give up on fetching data in block load requests, sequentially calculate addresses every 8 bytes, and send out the corresponding number of requests. Furthermore, even if the continuous data required by the request source is confined within one block boundary, the same problem as described above will occur if the leading and ending addresses do not match the block boundary. .

That is, even if the data is arranged continuously on the memory, it is only possible to efficiently fetch the data all at once using a block load request only when the data completely coincides with the block boundary.

[Means for solving problems]

In the memory access method of the present invention, the request source is
When attempting to obtain continuous data on a memory device all at once, a memory data request, the address of the first data in the data group, and the number of data transfers are instructed to the memory control device, and the memory control device receives the request. Transfer classification data corresponding to the originally designated start address is read out for the number of consecutive data transfers specified above, and transferred to the request source.

(Function) Therefore, the request source can obtain only the desired data at once and at high speed without worrying about the address positions of the beginning and end of the desired data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a data processing device to which the memory access method of the present invention is applied.

The data processing device of this embodiment includes an arithmetic control device 1 that is a request source, a memory control device 2, and a memory device 3. The request source may be a device that needs to read data from the memory device 3, such as an input/output device, in addition to the arithmetic control device 1 as in this embodiment. The memory device 3 may be a main memory device or a buffer memory that holds part of the data stored in the main memory device. It is assumed that the data transfer width between the arithmetic control unit 1, memory control unit 2, and memory device 3 is 8 bytes, and the memory block boundary is a 64-byte boundary.

First, the configuration of the arithmetic and control device 1 will be explained. The address register 10 is set with the address of the first data of the element data when the arithmetic and control unit 1 starts a data fetch operation. The request type register 12 is a register that holds various requests used by the arithmetic control device 1, such as request types such as 8B load/store and block load. In this embodiment, a request for instructing continuous fetching of operands is set. The request type set in the request type register 12 is converted into a request code by the encoder 16 and set in the request code register 15.

The element number register 11 is set with an initial value of the number of elements from which the arithmetic control unit 1 should fetch data. Adder 19 subtracts the value "8" from the number of elements set in element number register 11 to obtain the remaining number of elements. Adder 17 is address register 1
The value "64" is added to the address of 0 to find the start address of the next consecutive operand to be fetched.

The comparator 18 compares the number of elements set in the element number register 11 with the value "8", and outputs logic "1" if the number is greater than the value "8". "1" from comparator 18
When the is output, the address of the address register 10 is set in the address sending register 13. selector 32
When “1” is output from the comparator 18, the output from the adder 17 is set in the address register 10. selector 3
3 sets the output of the adder 19 in the element number register 11 when "l" is output from the comparator 18. When the comparator 18 outputs “1”, the selector 34 takes the value “8”.
is selected, and when "0" is output from the comparator 18, the number of elements in the element number register 11 is set in the transfer number sending register 14. The data receiving register 31 holds data transferred from the memory control device 2.

Next, the configuration of the memory control device 2 will be explained.

When the memory control device 2 becomes ready to accept memory requests, the lower 6 bits of the address sent from the address sending register 13 (representing an address within the block boundary) are set in the address register 21 through the selector 36, and the remaining upper bits are set in the address register 21. The address is set in the address register 20 through the selector 35. Further, the number of transfers sent out from the transfer number sending register 14 through the selector 37 is set in the transfer number register 22 . The number of transfers set in the transfer number sending register 14 is subtracted by "1" by the minus one circuit 27 every time one element data is read from the memory device 3, and is set in the transfer number register 22 through the selector 37. The OR circuit 29 performs the logical sum of all the bits of the minus one circuit 27, and detects whether the number of transfers has reached rQJ. The decoder 24 includes the request code register 15
When the contents of is decoded and the request for instructing continuous operand retrieval is decoded, logic "1" is set in the continuous operand retrieval instructing register 23, and the logic "1" is held thereafter until the operation of this request is completed. The adder 25 adds the value "8" to the address of the address register 21,
Update the address within the block. The plus one circuit 26 adds one to the address of the address register 20.

The selector 36 selects the output of the adder 25 when the output of the OR circuit 29 is "L", and selects the output of the OR circuit 29 or "0".
When this happens, the lower 6 bits of the address transferred from the address sending register 13 are selected and set in the address register 21. The AND circuit 28 outputs "l" when the operand continuous extraction instruction register 23 is set to logic "l", the output of the OR circuit 29 is "l", and the adder 25 outputs a carry. Selector 35 is AND circuit 2
When the output of 8 is "0", the address sent from the address sending register 13 is selected, and when it is "1", the output of the plus 1 circuit 26 is selected. When the adder 25 outputs a carry, the address selected by the selector 35 is set in the address register 20. The selector 37 selects the output of the minus 1 circuit 27 when the output of the OR circuit 29 is "L", and selects the output of the minus 1 circuit 27 when the output of the OR circuit 29 is "0", and selects the output of the transfer count sending register 1 when the output of the OR circuit 29 is "0".
Select the number of transfers from 4 and set it in the transfer number register 22. Data read from the memory device 3 is set in the data register 30.

Next, the operation of this embodiment will be explained.

Now, a fetch operation by which the arithmetic and control unit 1 processes the element data consecutively arranged from word number 4 to word number 13 as shown in FIG. 2 will be described. The size of one element data is 8 bytes, and in Figure 2 there are 10 bytes from element data 0 to element data 9.
Element data is continuously arranged from word number 4 to word number 13 in the address increasing direction.

When the data fetch operation is started in the arithmetic and control unit 1,
The start address of the element data, ie, the address corresponding to word number 4 where element data 0 is located, is set in the address register IO through the selector 32. Further, the number of element data to be processed, "lO" in this embodiment, is set in the element number register 11 through the selector 33. The number of elements set in the element number register 11 is compared with the value "8" by the comparator 18. If the number of elements is greater than 8, the comparator 1B sends out a logic "l", operates the selectors 32, 33, and 34, and selects the address register IO and the element number register 1.
1 and the contents of the transfer count sending register 14 are updated and set. That is, the address in the address register 10 is set in the address sending register 13, and
Adder 17 adds "64", selects it through selector 32, and stores it in address register lO as the start address of the next consecutive operand to be fetched.
Update the contents of. Furthermore, the element number register 11
The adder 19 subtracts "8" from the value and selects it through the selector 33 to update the contents of the element number register 11. The value "8" is selected and set in the transfer count sending register 14 through the selector 34. This means that
This indicates that the maximum number of transfers instructed from the arithmetic control unit 1 to the memory control unit 2 is r8'' (=64 bytes of data). However, this value is rl (=64
It is not fixed to the number of bytes), but can be set arbitrarily depending on the device. On the other hand, if the number of elements is 8 or less, the comparator 18 sends out a logic "0" and the address register 1
The contents of 0 are set in the address sending register 13, and the contents of the element number register 11 are selected through the selector 34 and set as they are in the transfer number sending register 14. Then, each of the address register IO and the element number register 11 enters a state of waiting for a new request according to an instruction from the comparator 18.

In this embodiment, the initial value of the number of elements set in the element number register 11 is "lO", which is greater than "8". Therefore, as mentioned above, the address register l
The address in O is set in the address sending register 13, and "64" is added by the adder 17, and updated as the start address of the next consecutive operand to be fetched. Further, "8" is set in the transfer count sending register 14, and the value of the element number register 11 is updated to the value obtained by subtracting "8" by the adder 19, that is, "2".

When the memory control device 2 becomes ready to accept requests, the contents of the address sending register 13, the transfer count sending register 14, and the request code register 15 are sent to the memory control device 2, respectively. Address sending register 1
The lower 6 bits of the address sent from address 3 are selected through selector 36 and set in address register 21. This address represents an address within a block boundary. The remaining upper addresses are selected through the selector 35 and set in the address register 20. The contents of the transfer count sending register 14 are selected through the selector 37 and set in the transfer count register 22. The contents of the request code register 15 are decoded by the decoder 24, the request for continuous operand retrieval instruction is decoded, and a logic ""
l" is set and held until the operation of this request is completed. At the same time, the arithmetic and control unit 1 sets the remaining 2
Preparations are made to send a request for fetching element data 8 and 9, which are element data. The element number register 11 holds a value "2" corresponding to the number of remaining two-element data to be fetched, and the comparator 1B compares it with the value "8" and outputs a logic "0". The request type register 12 continues to hold requests for instructions for continuous fetching of operands.
It is converted into a request code again by the encoder 16,
It is set in the request code register 15. At this point, the request type register 12 becomes empty for the first time, and is ready to accept a new request. Similarly, as described above, by sending out a logic "0" from the comparator 18,
Address register 10 and element number register 11
The contents of are set in the address sending register 13 and transfer count sending register 14, respectively, and the address register 10 and the number of elements register 11 are also placed in a state of waiting for new requests. Address sending register 13 for fetching the remaining two element data;
The contents set in the transfer count sending register 14 and the request code register 15 are respectively held until the memory control device 2 becomes ready to accept requests.

The memory control device 2 first accesses the memory device 3 using the addresses set in the address registers 20 and 21, and reads out the first element data 0. The read element data 0 is set in the data register 30 in the memory control device 2, transferred to the arithmetic control device 1 which is the request source, and set in the data receiving register 31.

In this way, the first element data 0 is read out from the memory device 3 and transferred to the arithmetic control device 1.
Subsequently, the following operation is performed in the same cycle as memory access to element data 0 is performed in order to read element data 1 following element data 0. The initial value "8" is set in the transfer number register 22, and this value is subtracted by one by the minus one circuit 27 to generate the value "7". This value is OR circuit 2
9, each bit is logically summed, and it is detected whether the value is 0 or not. If it is detected that it is not 0, the OR circuit 29 sends out a logic "l" and the selector 3
6. Operate the selector 37 and the AND circuit 28 to issue an instruction to generate a new starting address of the next consecutive element data. The value of the transfer count register 22 is updated to a value representing the remaining transfer count due to the memory access to element data 0.

In other words, the value "7" generated by the minus 1 circuit 27 is selected through the selector 37 and set in the transfer number register 22 at the timing when memory access to element data 0 is performed. The lower 6 memory addresses held by the address register 21 at the same timing
Adder 25 adds "8" to the bit value, and that value is selected through selector 36 and sent to address register 21.
Update the value of

This address represents a relative address within the block boundary and corresponds to word number 5 where element data 1 is located. The value of the address register 20 is determined by the AND circuit when the operand continuous retrieval instruction register 23 sends out a logic "1", the OR circuit 29 sends out a logic "1", and the adder 25 outputs a carry. Logic "1" is output at step 28, and the value obtained by adding 1 to the value of address register 20 at plus 1 circuit 26 is selected by selector 35 and updated. The adder 25 outputs a carry when the generated address exceeds a block boundary. In the address generation of element data 1, the address is generated within the same block boundary as element data O, and a carry is output. It is not output, and the value of the address register 20 remains as it was.

As described above, an address corresponding to element data 1 is generated, the memory device 3 is accessed, element data 1 is read out, and transferred to the arithmetic control unit 1. Thereafter, addresses for element data 2 and 3 are generated in the same manner, and element data 2 and 3 are sequentially read from the memory device 3 and transferred to the arithmetic and control device 1. When generating the address for element data 4, the adder 25 outputs a carry, and the value of the address register 20 becomes plus 1.
updated to the specified value. That is, it is updated to indicate the address of the next consecutive block data. Here, in the case of a normal block load request, since the operand continuous fetch instruction register 23 is not set, a logic "0" is output, and the output of the AND circuit 28 is also a logic "0", and the address register 23 outputs a logic "0". The value is not updated and remains the same. Therefore, the address indicated by address register 20 and address register 21 in this case indicates word number 0. In the case of a continuous operand extraction instruction request, the upper address held by the address register 20 is also updated to correspond to element data 4 of word number 8 according to the instruction from the operand continuous extraction instruction register 23.

In this way, the address of element data 4°5.6, which is the data on the next consecutive block data, is generated, and the corresponding element data is sequentially read from the memory device 3 and transferred to the arithmetic control unit 1. be done. When the memory access to element data 6 is performed, the values of address register 20 and address register 21 are updated to the value indicating element data 7, and the value of transfer count register 22 is set to the value "1" indicating the remaining transfer count. has been updated. In this case, the minus 1 circuit 27 generates and outputs "0", and the OR circuit 29 detects that the value is "0". When the value "0" is detected in the OR circuit 29, the OR circuit 29 sends out a logic "0" and the selector: 1
6, 37 and the AND circuit 28 to instruct the arithmetic and control unit 1 to prepare for accepting a new request. Then, it performs memory access to the memory device 3 to read the element data 7, and at the same time notifies the arithmetic and control unit 1 that the request can be accepted. At this time, the operand continuous fetch instruction register 23 is reset to logic "0". Element data 7 is read from memory device 3 and transferred to arithmetic control unit 1 through data register 30. The arithmetic control unit 1, which has been notified of the request acceptance state from the memory control unit 2, sends the address sending register 13. The request information prepared in the transfer count sending register 14 and the request code register 15 is sent to the memory control device 2. The memory control device 2 performs the same operation as described above to read the remaining element data 8 and 9 from the memory device 3 and transfers it to the arithmetic control device 1, thereby completing the series of operations for requesting a continuous operand retrieval instruction.

As a result of the above, word number 4 required by the arithmetic and control unit 1
Only the lO element data from element data 0 to element data 9, which are consecutively arranged from word number 1 to word number 13, are read from the memory device 3 and transferred to the arithmetic control device 1 that is the request source.

(Effects of the Invention) As explained above, in the present invention, the request source instructs the start address of the desired data and the number of transfers thereof, and the memory control device responds to the instruction, and the memory device responds to the specified address. By reading continuous data for the specified number of transfers from the above data and transmitting it to the request source, the request source does not have to worry about the start and end address positions of the desired data, etc. This has the effect of making it possible to obtain only desired data at once and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a data processing device to which the memory access method of the present invention is applied, and FIG. 2 is a schematic diagram showing a memory data format. 1...... Arithmetic control device, 2...
......Memory control device, 3...Memory device +0.20.21...Address register, 11
-・・・・・・・・・Element number register, 12
・・・・・・・・・・・・Request type register, 13
-------- Address sending register, 14
・・・・・・・・・Transfer count sending register, 15
・・・・・・・・・・・・Request code register,
16・・・・・・・・・Encoder, 17.19
．． 25--Adder, 18--Comparator, 22--Transfer count register,
23 --- Operand continuous retrieval instruction register, 24 --- Decoder,
26---------Plus 1 circuit 27...
・・・・・・Minus 1 circuit, 2 B −−−−−−・
...AND circuit, 29-------OR circuit, 30----------data register, 3
1... Data receiving register, 32~
37...Selector.

Claims (1)

[Claims] In a data processing device including a request source, a memory control device, and a memory device, when the request request source attempts to obtain continuous data on the memory device at once, the request source obtains memory data. The request, the address of the first data of the data group, and the number of data transfers are instructed to the memory control device, and the memory control device transfers consecutive data from the transfer category corresponding to the first address instructed by the request source. A memory access method that reads transfer classification data for the number of times of data transfer instructed and transfers it to the request source.