JPS58169269A - Data transfer control system - Google Patents

Abstract

PURPOSE:To transfer data consisting of plural words efficiently by editing the remaining data of words transferred previously and part of data of words to be transferred at this time and writing the resulting data in a storage device to which the data is designated for transferring. CONSTITUTION:The output of a byte mark pattern generator BMG and the contents of a byte mark preservation pattern generator BMGS and an alignment register ALGNR are determined uniformly by the value of a direction indicating flag DECF and the values of an address register A-REG and a length register LNGR. When a partial transfer deciding circuit PCCR decides on word-by-word transfer, a local storage LS transfers the remaining data of words transferred last and part of data of words to be transferred at this time to a data register D-RGG. Those data are edited according to the output of the BMG and the value of the ALGNR and the edited data are transferred from the D-REG to a main storage MG. Thus, data consisting of plural words is transferred efficiently.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention is based on a 5ffC system that allows data spanning multiple days to be efficiently transferred to a storage device in a short time even when the transfer start address does not exist on a word boundary. The present invention relates to a data transfer control method.

Conventional technology and problems〕 First! i! II shows an example of data transfer from local memory to main memory, where LB is local memory and M
8 indicates the main memory 0 In the illustrated example, iml
is 4 bytes, and 1 character is 1 byte. The right end shows the state of the main memory MB before data transfer, and the left end shows the state of local storage that stores the transferred data.

When the first 9 characters stored in the four-cal memory L8 are transferred to the main memory M8 using address 2 of the main memory MS as the transfer start address, the main memory MB after transfer is in the state shown in the center. become.

FIGS. 2(a) and 2(b) show conventional data transfer control systems. In the figure, [F] represents a lead and [
[Yes] indicates light. Note that it is assumed that data transfer as shown in FIG. 1 is performed. Figure 2 (a)
In this case, data transfer is performed using the following procedure.

■ Read lW# data [a baaJ from main memory MB.

■ Concatenate part of the read data with part of the data in p-cal memories I and S to create data "a b OIJ" and write this to the #1 word address of main memory MS. , the topmost word address in FIG. 1 is #1 word address.

■ Data [e] from #2 word address of main memory M8
Lead fghJ.

■ Part of the data output from IF and local recording tltL 8
data r 23g h J
and stores it at #2 word address of main memory M8.

■ Data r2 from #2 word address of main memory MB
Leading 3ghJ.

(2) Concatenate a portion of the read data and a portion of the data in the local storage Ls to create data r2345J, and write this to the #2 word address of the main storage MS.

■ Data r from #3 word address of main memory MS
1 jk, z Lead J.

■ Part of read data and local storage L81f'lf
-Create data "67kzJ" by connecting part of
Write this to the #3 word address of the main memory MS.

■ Data “6” from #3 word address of main memory MS
Leading 7klJ.

◎ Concatenate a part of the read data and a part of the data stored in the four-cal memory to create data "678/J" and write it to the #3 word address of the main memory MS.

In the case of Fig. 2←), data transfer is performed in the following five steps.

■ Data “a” from #1 word address of main memory Me.
Lead bcdJ.

■ Concatenate the read data and part of the data in the local memory L8, create data [abolJ, and store it in the main memory M
Write to #1 word address of S.

■ Data [e
Lead fghJ.

(2) Concatenate a part of the read data and a part of the local storage date data to create data "23gh" and store this in the #2 word address of the main memory MEI.

■ Write data "45" to bytes 2 and 3 of #2 word address of main memory MS. However, the leftmost byte is byte O.

■ Data ri from #3 word address of main memory MB
Lead jk/J.

(2) Concatenate a part of the read data and a part of the data in the local storage LS, create /Jt' in data r67, and write this to the #3 word address of the main storage M13.

■ Write data "8" to byte 2 of #3 word address of main memory MS.

In the conventional system shown in FIGS. 2(a) and 2(b), the transfer is done by partial or partial transfer, which has the disadvantage of being inefficient.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks and to provide a data transfer control method that can efficiently transfer data spanning multiple words even when the transfer start address does not exist on a word boundary. It is said that

[Structure of the invention]

For this reason, the data transfer control method of the present invention has a data transfer source storage device that stores the data to be transferred, a data transfer destination storage device that stores the transferred data, and an input side that is the data transfer source. a data register connected to the data output side of the storage device and the data output side of the storage device to which the data is transferred, and whose output side is connected to the data input side of the storage device to which the data is transferred;
π)-r- which controls the data register byte by byte.
a bytemark storage pattern generator that generates bytemark patterns that exceed word boundaries, a bytemark storage pattern generator that generates bytemark patterns that exceed word boundaries, and a bytemark storage pattern that holds the output of the bytemark storage pattern generator.・Register, holds the output of the above-mentioned bytemark pattern generator when transferring data for the first word, and when transferring data from the 21st I onwards, the output of the above-mentioned bytemark pattern generator and the above-mentioned bytemark storage pattern register'
Byte mark that holds the logical sum of the contents of
A length register that holds the amount of data transferred, an address register that holds the transfer start address, an align register that controls the alignment of transferred data, and whether or not it is a partial transfer based on the contents of the bytemark register. It is equipped with a partial transfer judgment circuit that determines the partial transfer, and a direction indicating flag that holds the address update direction at the time of transfer. The content is uniquely determined by the value of the direction flag, the address register, and the length register, and when the partial transfer determination circuit determines that the transfer is in word units,
A word unit created by editing the remaining data of the previously transferred word and part of the data of the word to be transferred this time according to the output of the above-mentioned byte mark pattern generator and the value of the align register. This data is characterized in that the data is written to the storage device of the transfer destination.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 3 is a diagram showing an overview of data transfer processing according to the present invention;
FIG. 4 is a diagram showing an example of the hardware configuration of the present invention, FIG. 5 is a diagram for explaining the processing according to the present invention, FIG. 6 is a time chart for explaining the present invention in detail, and FIG. The figure explains the store alignment, and the 8th @ is the fetch explanation.
FIG. 9, which is a diagram explaining alignment, is a diagram showing the relationship between each parameter.

FIG. 3 shows an overview of the processing of the present invention.

This process also assumes data transfer as shown in FIG.

■ Data “a” from #1 word address of main memory M8
Lead bcdJ.

■ A part of the read data and a part of the local storage L8 data are concatenated and the data is stored. Create "abol" and write it to #1 word address of main memory MB.

■ Edit the data in local storage and save the data [2345
Create J and write it to #2 word address of main memory MS.

■ Data [t] from #3 word address of main memory MS
, 1cjJ.

■ Concatenate the read data and part of the data in the local storage LS to create data ``6781J'' and store it in the main memory M.
l? Type in the #3 word address.

FIG. 4 shows an example of the hardware configuration of the present invention. In Figure 4, D-REG is a data 0 register, BMG is a bytemark pattern generator, BMR is a bytemark◆ register, BMSG is a bytemark storage pattern generator, BM8VR is a bytemark storage register, and ALGNR is an align register. , LNG'R is the length register, DIOF is the increasing direction flag, A
-REG indicates an address O register, large caR indicates a partial transfer determination circuit, and OR indicates a logical sum circuit.

Data register D-R1! :(]) It consists of 2.4 bytes. Bite mark pattern generator BM (N
A 4-bit byte mark pattern is generated, and the generated byte mark pattern is determined by the contents of the increment direction flag DIIF, length O register I, NGR, and address register A-RIG. The bytemark storage pattern generator BM8G generates a 4-bit bytemark storage pattern, and the values of the generated bytemark storage pattern are determined by the increasing direction flag DIIF, the length register LNGR, and the address register A-R1! ! Determined by the contents of G. The byte mark register BMR is a byte mark register.
This is a 4-bit register that holds a pattern obtained by ORing the bytemark pattern generated by the Patasen generator 11BMG or the bytemark pattern generated by the bytemark pattern generator BMG and the contents of the bytemark storage register BM8VR. The bits correspond one-to-one to each byte of a 4-byte wide word. That is, pi)O corresponds to pi)0, and bit 1 corresponds to byte 1. The same applies hereafter. Byte mark save register BMBvu is a 4-bit register that holds the pattern from the byte mark save pattern generator BMSG. Length register LNGR is a register that holds the amount of data transferred. Increase direction flag D
BCF indicates the data transfer direction. Address register Mu RBG holds the transfer address.
This register has 9 registers. Align register ALGN
R is a circuit for determining alignment during data transfer. A 0-part transfer determination circuit PCOR is a circuit for determining the unit of data transfer.

FIG. 7 illustrates store alignment. 7th
As can be seen, for example, align register ALGN
The RQ value is “Ol” and the value of the increasing direction flag DICOF is “
If bits 30 and 31 of the address are 0υ, byte 0°1.2 of data register D-RIG becomes byte 1.2.3 of main memory MS, and data register D-RIG becomes byte 1.2.3 of main memory MS.
Byte 3 of FIKG becomes byte O of main memory MS. Note that the address is a byte address.

FIG. 8 explains fetch alignment. As can be seen from Fig. 8, for example, align register ALG
If the value of NR is "Ol", the value of the increasing direction flag DliOF is "01", and the value of bits 30 and 31 of the address register is "01", bytes 1 and 2.3 of main memory M8 are data.・Register D-R1! ! G byte 0,1゜2
Therefore, byte 0 of main memory MS is data register D-
This becomes byte 3 of RIG.

FIG. 9 shows the relationship between each parameter. For example, increasing direction 7 lag D1nC! The value of F is rOJ.

If bits 30 and 31 of the address register are "10" and the length is "11", byte! - The byte mark pattern BM output by the pattern generator BMG is rllOQJ, and the byte mark storage pattern generator BM8
Bite mark saving putter output by G y BMli! V
is "0011", Boundary/RIS BDX is "l",
A. The line register LGNR will be "10".

The present invention will be specifically explained with reference to FIGS. 5 and 6. 5 and 6 assume a case where data transfer as shown in FIG. 1 is performed. In this case, the increasing direction flag I
1m! :OF is a mark, and address registers A-R
The initial value of IIIG is 2, and the length register L
The initial value of NGH is 9.

- When transferring word data, the increment direction flag is "0", bits 30 and 31 of the address are "lO", and the length is rll.
J, so the output of the byte mark pattern generator BMG is C byte mark storage pattern.
The output of the machine generator BMSG is 3, and each one is a byte! - is held in register BMR and byte mark storage register BMsVR. At this time, the bite mark
Since the contents of register BMH are not F (a pattern that indicates word-by-word transfer), the partial transfer determination circuit PCOR determines that it is a partial transfer, and sets the M8 write data from the local storage LB to the data register D-RIG. , the main memory Me, which holds part of the transferred data, is read, and the data aligned by the align register ALGNH is the byte of the byte mark O register BMR! - Riwo M
The byte mark inverted by the SN signal is set in the data register D-RIG, becomes transfer data for the - word, and is aligned and transferred to the main memory M8.

Next, when transferring data for the third word, the increase direction flag is set to “0”.
”, bits 30 and 31 of the address are “10”, and the length is “11”, so the output of the bytemark pattern generator BMG is 0 and the output of the bytemark storage pattern generator BMSG is 3.

The bytemark held in the bytemark register BMR is currently generated by the bytemark pattern generator B.
Pattern of MG occurrence and part-time job! - A logical sum of the patterns created and held in the storage register BM8VR is held. Also, the byte mark storage register BM8VR holds 3 which is currently generated by the byte mark storage pattern generator BM8G.

Since the content of the byte mark register BMR is 11, the partial transfer judgment circuit POC! indicates that it is a word transfer. R makes the decision. First, data for one word of local memory L8 is set in data register D-RIIiG in order to transfer the remaining portion of IW# of local memory LS, and then data for the third word of local memory L8 is transferred. Power data D = L8
The current bite mark pattern generator BMG is activated by the B signal.
data register D-R11 in a pattern where
! GK is set, aligned, and becomes the third word transfer data, which is transferred to the main memory MS as word unit transfer data.

Next, when transferring data for the third word, the increase direction flag is “0”
, bits 30 and 31 of the address are "10" and the length is "00", so byte mark pattern generator B
The output of MG is v8Y1. The output of turn generator BM8G is 0. At this time, the byte mark register BMR holds B, and the byte mark storage register BM8
VR holds 0.

In this case, the contents of the byte mark register BMR are v7
? Therefore, it is a partial transfer. Transfer data that is the remaining third word of local memory LB is transferred to data register D-R.
IG, and then the data to be transferred for the third word of local memory L8 is set in the data register D-RIG with the pattern currently being generated by the byte mark pattern generator BMG by the D=L8B signal. . next,
The main memory M8 is read, and the aligned data is transferred to the data register D- at the byte mark inverted by the MSN signal.
R1! tG, aligned as the third word transfer data, and transferred as the third word data in the main memory M8, and the operation ends.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, data spanning multiple words can be efficiently transferred to a storage device even if the transfer start address does not exist on a word boundary.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of data transfer from local storage to main memory, Figure 2 (a) ←) is a diagram explaining a conventional data transfer control method, and Figure 3 is a data transfer process according to the present invention. 4 is a diagram showing an example of the hardware configuration of the present invention. FIG. 5 is a diagram for explaining the processing according to the present invention. FIG. 6 is a diagram for explaining the details of the present invention. FIG. 7 is a diagram explaining store alignment, FIG. 8 is a diagram explaining fetch alignment, and FIG. 9 is a diagram showing the relationship between each parameter. L8...local memory, MEI...main memory, D-R
IG...data register, BMG...byte mark pattern generator, BMR...byte mark register, BM8G...byte, mark save pattern generator, BM8VR...byte mark save register, M I
, GNR...align fist register, LNGR...length register, DvCIF...increase direction flag,
A-RIG- Address register, POOR...
Partial transfer judgment circuit, OR...logical sum circuit. Patent Applicant: Fujitsu Co., Ltd. Patent Attorney Patent Attorney
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Claims (1)

[Claims] a data transfer source storage device that stores data to be transferred;
The data transfer destination storage device that stores the transferred data, the input side is connected to the data output side of the data transfer source storage device and the data output side of the data transfer destination storage device, and the output side is connected to the data transfer destination. A data register connected to the data input side of a storage device, a byte that generates a byte mark pattern that controls the data register on a byte-by-byte basis! a bytemark storage pattern generator that generates a bytemark pattern that exceeds a word boundary; a bytemark storage pattern register that holds the output of the bytemark storage pattern generator;
When transferring data for the first word, the output of the bytemark pattern generator is held, and when transferring data after the 2111th word, the output of the bytemark pattern generator and the contents of the bytemark storage pattern register are logically summed. a bytemark register that holds the amount of data transferred, a length register that holds the amount of data transferred, an address register that holds the transfer start address, an align φ register that controls the aignment of the transferred data, and the above-mentioned bytemark register.
It is equipped with a partial transfer determination circuit that determines whether or not it is a CIRI transfer based on the contents of the register, and a direction indicating flag that holds the address update direction at the time of transfer. The output of the save pattern generator and the contents of the align register are uniquely determined by the value of the direction instruction flag, the value of the address register, and the value of the length number register, and word-by-word transfer is performed by the partial transfer determination circuit. If it is determined that it is, the remaining data of the previously transferred Akebono and part of the data of the word to be transferred this time are edited according to the output of the note mark pattern generator and the value of the align register. The data transfer control method is characterized in that the word-by-word data edited and created is written to the transfer destination storage device.