JPS6111762Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a comparison control device in an analog control circuit.

Conventionally, the operation of this type of device was as shown in FIG. In the figure, V1 indicates the above set value, and when the input signal exceeds the upper limit set value, the comparison control device sends a "down" signal to the controlled object. V11
is the "down" signal stop value, and once the input signal exceeds the upper limit setting value V1, the "down" signal is sent out until the input signal reaches V11. Similarly, V2 is a lower limit set value, and when the input signal becomes less than the lower limit set value, the comparison control device sends a "lower" signal to the controlled object. V22 is the “raise” signal stop value,
Once the input signal falls below the lower limit set value V2, a "raise" signal is sent until the input signal reaches V22. That is, V1-V11 is the hysteresis of the "up" signal, and V22-V2 is the hysteresis of the "down" signal, and the target value in such a case is the intermediate value V3 between the upper limit setting value V1 and the lower limit setting value V2. If you want to reduce the frequency of operation and achieve stable operation, V11 and V22 may be set equal to V3, but conventionally, the hysteresis of this type of device is a constant value unique to the control device, and the upper limit setting value V1 or the lower limit setting value If V2 is changed, optimal control cannot be achieved, and in particular, in order to improve control accuracy, the upper limit set value V
1 and the lower limit set value V2 are set extremely close to each other, the "lower" signal stop value V11 will be lower than the lower limit set value V2, and conversely, the "raise" signal stop value V22 will be higher than the upper limit set value V1. There were problems such as the "down" signal and "up" signal being output at the same time. Especially when mechanical elements are involved, such as driving a setting motor with the output signal of a comparison control device, even if there are no electrical problems,
There were problems such as mechanical overshoot due to inertial force, leading to a hunting condition.

Further, when the output signal of the comparison control device is a contact signal from a relay or the like, there is a drawback that the service life is significantly shortened as the frequency of operation increases.

This idea was made in order to eliminate the drawbacks of the conventional ones as mentioned above.In the comparison control device, an intermediate value signal between both set values is always generated from the upper limit set value and the lower limit set value, and the optimum signal is generated. The purpose is to provide a device that can be controlled.

An embodiment of this invention will be described below with reference to the drawings. In Fig. 2, 1 is an input terminal, 2 is an input buffer amplifier, 3 is an input resistor of input buffer amplifier 2, 4 is a feedback resistor of input buffer amplifier 2, 5 is an upper limit setting device consisting of a variable resistor, and 6 is a variable resistor. 7 is an average value amplifier, 8 is an input resistor A of the average value amplifier 7, 9 is an input resistor B of the average value amplifier 7, 10 is a feedback resistor A of the average value amplifier 7, 11
is the average value amplifier 7 feedback resistor B, 1
2 is comparator A, 13 is input resistor A of comparator A,
14 is an input resistor B of the comparator A12, 15 is a diode that limits negative saturation of the comparator A12, 1
6 is the hysteresis setting resistor A of the comparator A12, 17 is the hysteresis setting resistor B of the comparator A12, 18 is the comparator B, 19 is the input resistor A of the comparator B, and 20 is the input of the comparator B. Resistor B, 21
22 is a hysteresis setting resistor A for the comparator B18, 23 is a hysteresis setting resistor B for the comparator B18, 24 is a comparator C, and 25 is a comparator C2.
4 is the input resistor A, 26 is the input resistor B of the comparator C24, 27 is the diode that limits the negative saturation of the comparator C24, 28 is the resistor A for setting the hysteresis of the comparator C24, 29 is the comparator 24 hysteresis setting resistor B, 30 is the inverter amplifier A, 31 is the input resistor of the inverter amplifier A30, 32 is the feedback resistor of the inverter amplifier 30, 33 is the inverter amplifier B, 34 is the input resistor of the inverter amplifier B33, 35 is the feedback resistor of the inverter amplifier B33, 3
6 is a differentiator A which generates a pulse at a positive edge, and is composed of a capacitor 37, a resistor 38, and a diode 39. 40 is differentiator B, capacitor 4
1, a resistor 42, and a diode 43.
44 is a differentiator C, a capacitor 45, a resistor 4
6, a diode 47, and 48 a differentiator D, which consists of a capacitor 49, a resistor 50, and a diode 51. 52 is R-S flip-flop A, 53
is an R-S flip-flop B, 54 is an output terminal A, and 55 is an output terminal B.

FIG. 3 is an explanatory diagram of the operation of an embodiment according to this invention, where V1 is an upper limit set value, V2 is a lower limit set value, and V
3 is an intermediate value between the upper limit setting value V1 and the lower limit setting value V2.

The detailed operation of this invention will be explained below with reference to the circuit diagram of an embodiment in FIG. 2 and the operation explanatory diagram in FIG. 3.

The input voltage introduced into the input terminal 1 is inverted in sign by an inverting amplifier circuit consisting of an input buffer amplifier 2, an input resistor 3, and a feedback resistor 4, and is sent to the input of each of the comparators 12, 18, and 24 in the next stage. Ru. Upper limit set value V obtained by upper limit setter 5
1 is introduced into one input of the comparator A12 and the average value amplifier 7. On the other hand, the lower limit set value V2 obtained by the lower limit setter 6 is introduced into each input of the comparator C24 and the average value amplifier 7.

The average value amplifier 7 has a gain of 1/1 with no sign reversal.
2 follower type configuration, the output V3 becomes V1+V2/2. Since the voltage applied to the input resistor A13 of the comparator circuit A12 is equal to the voltage applied to the input terminal 1 and only the sign is inverted, the comparator circuit A12 operates as long as the input voltage of the input terminal 1 is smaller than the upper limit setting value V1. Diode 1
5, and is clamped to approximately 0 [V]. At this time, the positive input terminal of comparator A12 has
Since the output voltage of the comparator A12 is divided by the hysteresis setting resistor A16 and the hysteresis setting resistor B17 and is fed back positively, the positive input terminal is approximately 0 [V]. When the input voltage at input terminal 1 increases and slightly exceeds the upper limit set value V1, the input terminal of comparator A12 becomes negatively biased, and due to the high open-loop gain and positive feedback of comparator A12, the output instantly Positively saturated. At this time, the positive input terminal of the comparator A12 is applied with the output voltage of the comparator A12 divided by the hysteresis setting resistors A16 and B17. If the input voltage becomes larger and the output becomes positively saturated, even if the input voltage becomes slightly smaller than the upper limit setting value V1, the output will not become 0 [V] and will remain positively saturated and the input voltage will reach the upper limit setting value. It inverts to 0 [V] only when it becomes smaller than V1 by the feedback voltage to the positive input terminal. In this case as well, due to the open loop again positive feedback of the comparator A12 until the limitation of the diode 15 is applied, the inversion is completed at once due to the high gain. Comparator B18, comparator C2
The operation of comparator A12 is also the same as that of comparator A12,
The difference is that the input level to be inverted is
Average value V3 of upper and lower limit settings and lower limit setting value V2
This is a point. Here, the hysteresis of each comparator is provided for stable operation of each comparison circuit, and can be arbitrarily selected using each hysteresis setting resistor, but normally a few [mV] to several tens [mV] is sufficient. , if the input voltage is 10 [V] at full scale
If so, the hysteresis of each comparator as seen from the input terminal will be about 0.1%. The inverter circuit consisting of the inverter amplifier A30, input resistor 31, and feedback resistor 32 inverts the output of the comparator B18, so when the input voltage is larger than the average value V3 of upper and lower limit settings, it saturates negatively, and when it is smaller, it saturates negatively. , approximately 0 [V]. Similarly, the inverter circuit consisting of the inverter amplifier B33, input resistor 34, and feedback resistor 35 inverts the output of the comparator C, so when the input voltage is larger than the lower limit set value V2, it is negatively saturated, and when it is smaller, it is approximately 0
It becomes [V]. Each differentiating circuit 36, 40, 44, 4
8 generates a pulse of positive polarity at the time of inversion from 0 [V] to a positive voltage or from a negative voltage to 0 [V], that is, at a positive edge. Therefore R-
The set input terminal of the S flip-flop 52 is
When the input voltage becomes slightly larger than the upper limit set value V1, a positive polarity pulse is applied to set the R-S flip-flop 52, and the input voltage gradually decreases until it becomes slightly larger than the upper and lower set average value V3. When the voltage becomes small, a positive pulse is applied to the reset input terminal of the R-S flip-flop 52, and the R-S flip-flop 52 receives a positive pulse.
-S flip-flop 52 is reset. R
When the input voltage becomes smaller than the lower limit set value V2, a positive pulse is applied to the set input terminal of the -S flip-flop 53, the R-S flip-flop 53 is set, and the input voltage gradually increases to set the upper and lower limits. When it becomes slightly greater than the average value V3, a positive pulse is applied to the reset input terminal of R-S flip-flop 53, and R-S flip-flop 53 is reset. The output of each flip-flop 52, 53 is connected to an output terminal 54.
and output to the output terminal 55 as a "lower" signal and a "higher" signal.

In the above embodiment, a limiting diode was added to protect the input of the comparator, but it may be removed if the comparator has a protection function or other protection is not necessary. Although it is composed of capacitors, resistors, and diodes, it goes without saying that it can be replaced with a one-shot multivibrator or other device with equivalent functionality.Furthermore, the R-S flip-flop can also be used as a latch circuit to achieve the same effect. play.

As described above, according to this invention, in the comparison control device, an average value is created from the upper limit set value and the lower limit set value, and the hysteresis of the device is set to half the difference between the two set values. Regardless of the size of the difference, the control always drives toward the control target value, improving control accuracy and significantly reducing unnecessary operations, making the equipment more stable and significantly extending its life. There are effects such as:
Furthermore, since optimal hysteresis can be obtained even if the upper limit set value and lower limit set value are very close to each other, there is an advantage that operation close to constant value control can be performed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the operation of a conventional comparison control device, FIG. 2 is a circuit diagram showing an embodiment of the comparison control device according to this invention, and FIG. 3 is an explanatory diagram of the operation of the embodiment of FIG. 1 is an input terminal, 2 is an input buffer amplifier, 5 is an upper limit setter, 6 is a lower limit setter, 7 is an average value amplifier, 12 is a comparator A, 18 is a comparator B, 2
4 is comparator C, 30 is inverter amplifier A, 33
is inverter amplifier B, 36 is differentiator A, 40 is differentiator B, 44 is differentiator C, 48 is differentiator D, 5
2 is an R-S flip-flop A, 53 is an R-S flip-flop B, 54 is an output terminal A, and 55 is an output terminal B.

Claims (1)

[Scope of utility model registration request] In a comparison control device equipped with an upper limit setter and a lower limit setter, an average value circuit generates an average value of both set values from the upper limit set value by the upper limit setter and the lower limit set value by the lower limit setter, and the input signal is set at the upper limit setter. A comparator that detects that it is larger than the upper limit set value by the setter, a comparator A that detects that it is larger than the upper limit set value by the setting device, and a comparison that determines whether the input signal is larger or smaller than the average value of the above average value circuit. A comparator B detects that the input signal is smaller than the lower limit setter, and a comparator C is set based on the detection signal of the comparator A when the input signal becomes larger than the upper limit set by the setter. a flip-flop A which is reset based on the detection signal of the comparator B when the input signal becomes smaller than the average value of the average value circuit; When the input signal is smaller than the lower limit set value, it is set based on the detection signal of the comparator C and outputs a raise signal, and when the input signal becomes larger than the average value of the average value circuit, the comparator 1. A comparison control device comprising a flip-flop B that is reset based on a detection signal of B.