JPS61117260U - - Google Patents
Info
- Publication number
- JPS61117260U JPS61117260U JP1985000733U JP73385U JPS61117260U JP S61117260 U JPS61117260 U JP S61117260U JP 1985000733 U JP1985000733 U JP 1985000733U JP 73385 U JP73385 U JP 73385U JP S61117260 U JPS61117260 U JP S61117260U
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- semiconductor device
- recess
- mounting surface
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
第１図は、本考案の一実施例による半導体装置
の斜視図、第２図は第１図の半導体装置の断面図
、第３図は、従来の半導体装置を外部放熱板にネ
ジ止めした時の斜視図、第４図は、従来の他の半
導体装置を外部放熱板にネジ止めした時の斜視図
である。 １……放熱板、２……放熱板の取付けネジ穴部
、３……凹部、４……モールド樹脂、６……ネジ
、５……外部電極端子、７……押え金具。
の斜視図、第２図は第１図の半導体装置の断面図
、第３図は、従来の半導体装置を外部放熱板にネ
ジ止めした時の斜視図、第４図は、従来の他の半
導体装置を外部放熱板にネジ止めした時の斜視図
である。 １……放熱板、２……放熱板の取付けネジ穴部
、３……凹部、４……モールド樹脂、６……ネジ
、５……外部電極端子、７……押え金具。
Claims (1)
- 放熱板を備えた半導体装置において、該放熱板
部のネジ取付部が、該放熱板部の外部放熱板への
取付面にへこみを有する凹形形状をしていること
を特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985000733U JPS61117260U (ja) | 1985-01-08 | 1985-01-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985000733U JPS61117260U (ja) | 1985-01-08 | 1985-01-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61117260U true JPS61117260U (ja) | 1986-07-24 |
Family
ID=30472842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985000733U Pending JPS61117260U (ja) | 1985-01-08 | 1985-01-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61117260U (ja) |
-
1985
- 1985-01-08 JP JP1985000733U patent/JPS61117260U/ja active Pending