JPS61116860A - Formation of multilayer interconnection of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the electrically good condition of connection by connecting the lower layer wiring Al with the upper layer wiring Al through an TiO2 film by spreading the lower layer wiring Al and subsequently coating it with Ti which is hard to be oxidized compared with Al. CONSTITUTION:An Al or Al-Si layer 2a on an Si substrate 1 is coated with Ti 7 and the surface is covered with TiO2 8. Then it is connected with the Al or Al-Si layer 5 as an upper layer through a through hole 4 of an interlaminar insulating film 3. At this time, TiO2 is deoxidized by Al and Ti and Al produce a connection part of metals so that the electrically good energizing condition can be obtained in this part. In addition to Ti, it is possible to use a simple substance or an alloy of Cr, Si, Fe, Mg, Zn, Ni, Cu, Pd, Pt, Au, Sn, Pb and Mn. By this method, even if the through hole is extremely minute, the upper (5a) and lower wiring layers are connected well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for forming multilayer wiring in a semiconductor integrated circuit that requires a high degree of integration.

[Prior art and its problems]

Generally, multilayer wiring in an integrated circuit is performed through the steps shown in FIGS. 2A to 2F. In other words, FIG. 2 shows, for example, in the case of two-layer wiring, an Al or Al-81 layer 2 is formed on a Si substrate 1.
Step 1) of forming the first layer of wiring 2a by vapor depositing and using a normal photo-etching method.

5102 * Step of forming an interlayer insulating film 3 such as PSG, Si 3N4 (0, Step of forming a through hole 4 in the glabella insulating film 3 for contacting with the second layer wiring 0, Second layer AJ'' Alternatively, it consists of a step of vapor depositing the AJ-8i layer 5 [F] and forming the second layer arrangement 5a by photo-etching.

However, in the process of forming the conventional multilayer wiring as described above, an oxide film A12036 of AI is generated on the surface of the first layer wiring 2a, as shown in FIG.
AJ or 1- is deposited after forming the through hole 4.
The 8i layer 5 is actually deposited on the kl 2036, and the connection between both fls2a and 5a through the through hole 4 is not an AI-to-AI connection as shown in FIG.
Since the contact is Oa, a good connection state cannot be obtained. Therefore, attempts are generally made to remove the A7203 film 6 that is naturally generated on the surface of the grain size 1j12a by some method, but since the Al oxide film is extremely stable, it is difficult to remove it by chemical treatment. Therefore, physical methods such as spatter removal are often used, but even this method is not always perfect. When AI is used for 2a and A1 alloy containing a metal that is more oxidizable than the material Kd of the second layer wiring 5a is used to connect the two, an AJ203 film 6 is formed on the first layer wiring 2a. For example, it is disclosed in JP-A-59-46047 that a good electrical connection can be obtained because the second layer wiring alloy is reduced, but in this case as well, the composition ratio of the alloy is controlled by vapor deposition. Metals that are difficult to oxidize and are easily oxidized as well as AI, which is the Q1 alloy component, are limited to Ca, Mg, etc., and there is a risk that these may be mixed in as mobile ions that have an adverse effect on semiconductor devices.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for forming multilayer wiring that can easily obtain a good electrical connection state by eliminating connection failures between wirings caused by films. .

[Key points of the invention]

In the present invention, after the lower layer wiring AI has been deposited, a K-resistant metal that is oxidized by M, such as T1, is subsequently deposited, and the upper layer wiring U is deposited on the metal oxide film formed on this deposited surface. By making the connection between the two wirings sandwich this metal, the
Since the TiO2 oxide film generated in the above is reduced by the upper layer wiring M, many metal-to-metal connections are formed between the two wirings, resulting in a good electrical connection between the wirings. It is.

[Embodiments of the invention]

The present invention will be explained below based on examples.

FIGS. 1A to 1F show the manufacturing process of, for example, two-layer wiring, to which the method of the present invention is applied, in conjunction with FIGS. 2A to F, and each process in both figures substantially corresponds to each other. However, the difference that is particularly relevant to the present invention is that in FIG. 1A, KAA! Or after depositing Al-3i layer 2,
Immediately, without giving time for these oxide films to be formed on the surface of the υ or AI-st layer 2 (depositing the Ti film 7), the subsequent steps are the same as in the case of Fig. 2. Step Q3) of forming the first layer wiring 2a by a normal photoetching method; Step C) forming the low temperature oxide film 3 as the first interlayer insulation film; Step (2) of forming a through hole 4 to obtain a contact, vapor deposition of a second layer of Ai or All-8i layer 5 [F], and step of forming a second layer wiring 5a by photoetching [F] Consisting of

According to the above process of the present invention, as shown in FIG. 1B, the oxide film A shown in FIG. 2B is formed on the first layer wiring M or Al-8iZa! 2036 is not produced, and the oxide film naturally produced through this process is coated on the exposed surface of the Ti film 7 as T iQ 2 B. Therefore, even if there is an oxide film on the first layer wiring 2a in the through hole 4, since this oxide film is Ti oxide Tie2, the contact with the second layer AI or AJ-8i layer 5 is A
It is done between TlO28 and not ll203.

At this time, a reaction based on the following equation occurs between the Tie 28 and, for example, the AI layer 5.

3 T 102 + 4 kF-m-T 1 + 2
AA! 203 (1) That is, TiO2 is AA
! Since the Ti and Al metals are reduced and a connection portion is formed between the metals, a good electrical conduction state can be obtained at that portion.

From this, it can be concluded that gold ingots to be continuously deposited on the first Al or Al-8i layer 2 are those in which the redox reaction of equation (1) proceeds on the right side, that is, those that are less oxidizable than AI. It can be seen that the material is not limited to TI but may be other metals as long as they are suitable. For example, Cr+Si+Fet
Mg, Zn, Ni, Cu, Pd, Pt, Au, Sn, P
b, Mn, etc., and these may be used as a single metal or an alloy, or may be used as a stack of multiple metals. The material should be selected according to the actual situation, taking into consideration the fact that the oxide film 6 is deposited on the layer 2 before it is formed, and the characteristics, vapor deposition, and photoetchability of these metals or alloys themselves. is necessary. In this case, for example, T is applied to the All or Al-8a layer 2.
The film thickness of iJIIE7 is determined by Alt & AI- during this process.
Since A12036 that is naturally generated on the surface of the Si layer 2 is usually 40 to 50X thick, it is necessary to have a thickness larger than that.
It is sufficient to have about 100X, but it may be more if there is no problem with photoetching properties. In the method of the present invention, an appropriate film thickness of 1°0~zooX
^1 preferred.

In this example, the case of two-layer wiring was explained, but
For example, it goes without saying that the method of the present invention can be applied to each wiring layer except for the uppermost layer even in the case of multilayer wiring of three or more layers.

〔Effect of the invention〕

As explained in the embodiments above, when forming multilayer interconnects for semiconductor integrated circuits, conventional connections between upper and lower interconnect layers are due to the oxide film formed on the lower interconnect layer, resulting in bonding between similar metals and their oxides. Therefore, it was not possible to obtain a good electrical connection state. However, according to the method of the present invention, by depositing a metal on the lower wiring layer that is less likely to be oxidized than the wiring metal, Since the oxide film is generated not on the lower wiring layer but on the deposited metal above it, the lower wiring deposited metal and upper layer wiring are formed at the connection part with the upper wiring layer based on the oxidation-reduction reaction between the upper and lower wiring layers. As a result of forming metal-to-metal joints, good electrical connection can be achieved between the multilayer wiring.

Therefore, when using the method of the present invention, even if the diameter of the through hole is extremely small, metal-to-metal bonding is achieved in both the upper and lower wiring layers, resulting in a favorable connection state, which will further reduce power consumption and increase It has the advantage that it can sufficiently respond to the trend of semiconductor integrated circuits that require higher integration, and that the manufacturing method is simple.

[Brief explanation of drawings]

FIG. 1 is a process diagram for forming a multilayer wiring using the method of the present invention, and FIG. 2 is a process diagram for forming a flat multilayer wiring using a conventional method. 1...St substrate, 2, 5...AI or Al-8a layer.

Claims (1)

[Scope of Claims] 1) When performing multilayer wiring of a semiconductor integrated circuit, after forming a lower layer wiring metal on a semiconductor substrate, a metal film having a weaker oxidation property than the lower layer wiring metal is formed on the lower layer wiring metal. coated,
Next, an interlayer insulating film and a through hole penetrating the interlayer insulating film are formed on the metal film, and an upper layer wiring metal is formed on the interlayer insulating film to be deposited on the metal film through the through hole. A method for forming multilayer wiring for a semiconductor integrated circuit. 2) A method for forming a multilayer wiring for a semiconductor integrated circuit, characterized in that in the method according to claim 1, Al or Al-Si is used as both the upper and lower wiring metals. 3) In the method according to claim 1 or 2, the metal film may include Cr, Ti, Si, Fe, Mg, Zn,
A method for forming a multilayer wiring for a semiconductor integrated circuit, characterized in that at least one of Ni, Cu, Pd, Pt, Au, Sn, Pb, and Mn is used.