JPS61111472A - Large scale integrated circuit test system - Google Patents

Abstract

PURPOSE:To execute easily test a by using a test mode indicating terminal for the test of a built-in read/write storage circuit and changing a terminal to be used only for outputs to a two-way terminal. CONSTITUTION:When a test mode indicating signal 102 is turned to '1', a test mode indication NOT signal 103 is turned to ''0''. When a test mode is excited, buffers 9, 11 are activated, two-way signals 110, 111 are inputted and two-way input buffer signals 112, 113 are supplied to a data selecting circuit 3 and an address supplying circuit 5 respectively as the data and address of the read/write storage circuit 6 and output signals 105, 107 are supplied from the circuits 3, 5 to the circuit 6 as the data and address. When a writing signal 101 is activated, the data are written and stored in the circuit 6. A shift signal 115 for shifting only a reading register circuit 13 is added at the reading of data in case of the test mode to shorten reading. Since the signal 102 and the shift signal 115 are added and the terminal to be used as an output terminal is switched to a two-way terminal, the circuit 6 can be easily tested and the data can be read out rapidly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a test system for performing a test mode of a read/write storage circuit.

In the prior art, it is extremely difficult to test memory circuits such as random access threat files and register files unless data, addresses, and write signals are directly supplied from external terminals.

Problems to be Solved by the Invention However, in a memory circuit included in a large-scale integrated circuit, data and address signals are normally supplied to the memory circuit through several to more than ten stages of circuits69, and it is easy to test. In order to directly supply data address and write signals from external terminals only for testing, there is a limit to the number of input/output terminals that large-scale integrated circuits have, and it is not possible to provide terminals only for testing. Almost impossible. Furthermore, there is a drawback that it takes a long time to read out data by operating all seven footpaths in the data extraction operation from the read/write circuit.

Item Axis E1 The object of the present invention is to eliminate the drawbacks of the prior art, to facilitate the testing of read/write storage circuits, and to read data using minimum shift operations. Our goal is to make everything easier.

Means for Solving the Problems The system of the present invention provides a test mode instruction terminal for receiving a signal indicating a test mode and a read/write memory circuit in a large-scale integrated circuit test system having a read/write memory circuit. a data supply circuit that supplies data to the data supply circuit; a selection circuit that selects an output signal of the data supply circuit and a bidirectional terminal input signal in response to the test mode instruction signal; and a selection circuit that supplies an address to the read/write storage circuit. an address supply circuit to supply, a selection circuit that selects an output signal of the address supply circuit and a bidirectional terminal input signal according to the test mode instruction signal, and a write signal circuit that writes data to the supplied address. A read register circuit that stores the output signal of the read/write memory circuit, a shift pass circuit that chains all 7 lips, and a shift operation of only the successive register circuit when performing a read operation of the read/write memory circuit. The present invention is characterized in that it has a continuous output/write storage circuit shift terminal that receives a signal instructing the read register circuit, and a path that directly outputs the shift act data of the read register circuit to the final output.

Operation To test the read/write memory circuit built into a large-scale integrated circuit, a test mode instruction terminal is prepared, and the terminals originally used only as output terminals are changed to bidirectional terminals to increase the number of terminals for testing. Using a circuit scheme that can easily provide data, address, and write signals for the read/write storage circuit without increasing the read/write storage circuit allows easy testing of the read/write storage circuit.

Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment includes a NOT circuit 1, a data supply circuit 2, a data selection circuit 3, an address supply circuit 4, an address selection circuit 5, a read/write storage circuit 6, a logic circuit group 7, a first bidirectional output buffer 8, a first bidirectional input buffer 9, a second bidirectional output buffer 10, a second bidirectional input buffer 7a 11, NOT circuit 12 , read register circuit 13 , first register circuit 14 , second register circuit 15 , and selection circuit 16
including.

The write signal 101 is input to the read/write storage circuit 6,
The test mode instruction signal 102 is applied to the NOT circuit 1, the data selection circuit 3, the address selection circuit 5, the first dual doujin cap 7a 9, and the second dual doujin cap 7a 111C. The test mode instruction negation signal 103, which is the output signal of the negation circuit 1, is given to the data selection circuit 3, the address selection circuit 5, the first bidirectional output rose 778, and the second bidirectional output buffer 10 to supply data. Output signal 1 of circuit 2
04 is input to the data selection circuit 3. The output signal 105 of the data selection circuit 3 is input to the read/$include storage circuit 6. The output signal 106 of the address supply circuit 4 is input to the address selection circuit 5, and the output signal 107 of the address selection circuit 5 is supplied to the read/write storage circuit 6.

The output signal 108 of the logic circuit group 7 is applied to the first bidirectional output buffer 8 , and the output signal 109 is similarly inputted to the second bidirectional output buffer 10 . Bidirectional signal 110
is input to the first bidirectional output buffer 9, and the bidirectional signal 111 is provided to the second bidirectional large cover 7a 11.

The output signal 112 of the first bidirectional white capacitor 7a 9 is input to the data selection circuit 3, and the output signal 113 of the second bidirectional manual buffer 11 is applied to the address selection circuit 5. The shift-in signal 117 is input to the data supply circuit 2, the shift-out signal 118 of the data supply circuit 2 becomes the shift-in signal of the address supply circuit 4, and the shift-out signal 119 becomes the shift-in signal of the read register circuit 13. . Similarly, the shift-out signal 120 is input to the shift-in signal and selection circuit 16 of the first register circuit 14, and the shift-out signal 121 of the first register circuit 14 becomes the shift-in signal of the second register circuit 15. Similarly, the shift-out signal 122 becomes an input signal to the selection circuit 16. The output signal 114 of the read/write memory circuit 6 is inputted to the read register circuit 13 (-1). The output signal 116 of the NOT circuit 12 is sent to the selection circuit 16.
The output signal 123 of the selection circuit 16 is supplied to the next stage circuit.

In normal operation, test mode indication signal 102 is I
O'', the output signal 104 of the data supply circuit 2 is applied as the write data to the read/write storage circuit 6 via the data selection circuit 3 as the output signal 105.
The output signal 106 of the address supply circuit 4 is given as the address of the read/write memory circuit 6 via the address selection circuit 5 as the output signal 107, and becomes the write signal 101, and data is stored in the read/write memory circuit 6. be remembered.

However, when testing read/write storage circuits, it is difficult to set and test data and addresses through the paths used in normal operation.

This is because when testing, data or addresses are supplied to the read/write memory circuit by setting values to the external terminals, but the values cannot be sent from the external terminals until the data supply circuit 2 and address supply circuit 4. Since the number of circuit stages is multi-stage, it is necessary to perform various controls in order to secure the transmission path along the way. Further, it is difficult to newly provide an address supply terminal or a data supply terminal just for testing because the input/output terminals of a large-scale integrated circuit are limited.

Therefore, in the present invention, terminals that are originally used only as output terminals and are not relevant when testing the read/write memory circuit are changed to bidirectional terminals, and the test mode instruction terminal signal 102 and the read/write memory circuit are changed into bidirectional terminals. The purpose is to add the circuit shift signal 115 to easily test the read/write memory circuit 6 and read data at high speed.

When the test mode instruction signal 102 becomes w11', the test mode instruction negation signal 103 becomes mol.

When the test mode is entered, the first bidirectional input buffer 7 and the second bidirectional input buffer 11 become active.
First bidirectional signal 110 and second bidirectional signal 111
becomes the input signal and the first two-way doujin cover sofa signal 11
2 and a second bidirectional human buffer signal 113 are provided as data and address of the read/write storage circuit 6, respectively. An output signal 105 is supplied as data via the data selection circuit 3, and an output signal 107 is supplied as an address via the address selection circuit 5. At that time, when the write signal 101 becomes active, data is written and stored in the read/write storage circuit 6.

Furthermore, as a method of reading data written in the read/write memory circuit, all 7 lips and 70 pieces are often read out by chained shift operations, but in normal shift operations, it is necessary to perform an extra shift operation. Therefore, it takes time to read data.

Therefore, a read/write memory circuit shift signal 115 is added that enables only the read register circuit 13 to perform a shift operation when data is continuously output during a test of the read/write memory circuit. shorten the reading time.

In this way, by adding the test mode instruction signal 102 and the read/write memory circuit shift signal 115, the terminal that is originally used as an output terminal and is not relevant when testing the read/write memory circuit 6 is changed into a bidirectional terminal. In particular, it becomes possible to easily test the read/write memory circuit 6 and to read data at high speed, making it easy to test the entire large-scale integrated circuit and confirm whether the circuit is defective based on detailed test results. This can lead to improved reliability of large-scale integrated circuits.

ADVANTAGEOUS EFFECTS OF THE INVENTION The present invention has the advantage that testing of read/write memory circuits built into large-scale integrated circuits can be facilitated with only a minimal increase in external terminals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. In Fig. 1, 1...Negation circuit, 2...
...Data supply circuit, 3...Data selection circuit,
4...-address supply circuit, 5...address selection circuit, 6...read/write storage circuit, 7
...Logic circuit group, 8...1st
10 bidirectional output ``''''・9-°-10th bidirectional human cover 7a, 10...second bidirectional output buffer, 11...second bidirectional white cover 7 A, engineering 2
.--Negation circuit, 13...Read register circuit, 14...-first register circuit, 15...
...Second register circuit, 16...Selection circuit, 101...Write signal, 1o2...
Test mode instruction signal, 1o3... Test mode instruction negation signal, 104... Data supply circuit output signal, 105... Data supply signal, 106...
...Address supply circuit output signal, 107...
...Address supply signal, 108...First logic circuit group output signal, 109...Second logic circuit group output signal, 110...First bidirectional signal signal, 11
1...Second bidirectional signal, 112...
First bidirectional manual buffer signal, 113...Second bidirectional white cover signal, 114...-Read/write storage circuit output signal, 115...Read /Write memory circuit shift signal, 116...Read/write memory circuit shift negation signal, 117...Shift-in signal, 118...Data supply circuit shift-out signal, 119... Address supply circuit shift out signal, 120... Read register circuit shift out signal, 121... First register circuit shift out signal, 122... - Second register circuit shift out signal, 123...selection circuit output signal.

Claims (1)

[Claims] In a large-scale integrated circuit test system having a read/write memory circuit, a test mode instruction terminal receives a signal instructing a test mode, and a data supply circuit supplies data to the read/write memory circuit. a selection circuit that selects an output signal of the data supply circuit and a bidirectional terminal input signal in response to the test mode instruction signal; an address supply circuit that supplies an address to the read/write storage circuit; a selection circuit that selects the output signal of the address supply circuit and the bidirectional terminal input signal in response to the test mode instruction signal; a write signal circuit that writes data to the supplied address; and the read/write circuit. A read register circuit that stores the output signal of the write memory circuit, a shift pass circuit that chains all the flip-flops, and a signal that instructs only the read register circuit to perform a shift operation when performing a read operation of the read/write memory circuit. 1. An integrated circuit test system comprising: a read/write storage circuit shift terminal for receiving a read/write storage circuit; and a path for outputting shift-out data of the read register circuit directly to a final output.