JPS61107837A - Time division multiplex communication equipment - Google Patents
Time division multiplex communication equipmentInfo
- Publication number
- JPS61107837A JPS61107837A JP23061884A JP23061884A JPS61107837A JP S61107837 A JPS61107837 A JP S61107837A JP 23061884 A JP23061884 A JP 23061884A JP 23061884 A JP23061884 A JP 23061884A JP S61107837 A JPS61107837 A JP S61107837A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transmission
- communication
- line
- branch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/08—Intermediate station arrangements, e.g. for branching, for tapping-off
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明け′り話、データ及び画像情報等をディジタル
化して時分割多重化方式により伝送する通信装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] This invention relates to a communication device that digitizes stories, data, image information, etc. and transmits them using a time division multiplexing method.
第8図は従来回路により、端末機器の情報を中継する回
路構成例であり、図において(1)は伝送路Aに接続さ
する装置、(21は伝送路Bに接続さnる装置、(3)
は端末機器、(4)は端末機器接続回路、(5)は送信
デ°−々バス、(6)は受信データバス、(8)は伝送
路接続回路、(9)はタイミング発生回路、αGは監視
制御回路、(1)は端末信号中継接続装置である。FIG. 8 is an example of a circuit configuration for relaying information from terminal devices using a conventional circuit. In the figure, (1) is a device connected to transmission path A, (21 is a device connected to transmission path B, 3)
is the terminal equipment, (4) is the terminal equipment connection circuit, (5) is the transmission data bus, (6) is the reception data bus, (8) is the transmission line connection circuit, (9) is the timing generation circuit, αG 1 is a monitoring control circuit, and (1) is a terminal signal relay connection device.
次に動作について説明する。伝送路Aからの受信データ
は装置(1)に接続さn、伝送路接続回路(8)で伝送
路符号(例えばCMI符号、Code Mark、In
version )からHR’z符号(Hon −Re
turn t。Next, the operation will be explained. The received data from the transmission path A is connected to the device (1), and the transmission path connection circuit (8) converts the data into a transmission path code (for example, CMI code, Code Mark, In
version ) to HR'z code (Hon-Re
Turn t.
Zero)等に変換し、さらに受信デー々のフレーム
□同期とクロック抽出を行なった後の受信データ
を受信パス(6)に接続し、その後、端末機器接続回路
(4)を経て、端末機器(3)へ接続さする。一方端末
機器(3)からの送信データは、端末機器接続回路(4
)、送信デー少パス(5)を経て、伝送路接続回路(8
)で伝送路符号に変換さn、伝送路Aへ送出される。タ
イミング発生回路(9)と監視制御回路Qd 1.?装
置(1)が正常動作を行なうための共通部であり、タイ
ミング発生回路(9)は複数の端末機器接続回路(4)
がらの送受信データを送信データバス(5)、受信デー
タバス(6)に入出力するタイムスロットを制御し、ま
た監視制御回路αdは装置の警報動作表示を制御する椰
能を有す。Zero), etc., and then convert the frames of the received data.
□The received data after synchronization and clock extraction is connected to the reception path (6), and then connected to the terminal device (3) via the terminal device connection circuit (4). On the other hand, the transmission data from the terminal device (3) is sent to the terminal device connection circuit (4).
), the transmission path connection circuit (8) via the low transmission data path (5)
) is converted into a transmission path code n and sent to transmission path A. Timing generation circuit (9) and supervisory control circuit Qd 1. ? It is a common part for the device (1) to operate normally, and the timing generation circuit (9) is a common part for multiple terminal equipment connection circuits (4).
The supervisory control circuit αd has the function of controlling the time slots for inputting and outputting the transmitted and received data to and from the transmit data bus (5) and the receive data bus (6), and also controls the alarm operation display of the device.
伝送路Bからの送受信データは9 置(21に接続さ釘
、上記と同様の動作を行なう。Transmission and reception data from transmission path B is connected to the 9th position (21) and performs the same operation as above.
伝送路Aと伝送路3間の端末情報を中継する場合は、端
末お器接続回路(4)からの送受信データを端末信号中
継接続装置(1)で中継接続する。When relaying terminal information between the transmission path A and the transmission path 3, the transmission/reception data from the terminal device connection circuit (4) is relayed by the terminal signal relay connection device (1).
従来の時分割多重化装置は以上のように構成さ1ている
ので、複数の伝送路間で信号の中継を行なう場合は、中
継する端末機器の数量だけ端末機体接続回路(4)をも
つことが必要であり、また端末信号中継接続装@(ホ)
も必要であり、システム構成上、機器構成が多く高価に
なる問題点があった。Conventional time-division multiplexing equipment is configured as described above1, so when relaying signals between multiple transmission lines, it is necessary to have as many terminal device connection circuits (4) as there are terminal devices to be relayed. is required, and a terminal signal relay connection device @(E) is required.
However, in terms of system configuration, there are problems in that the system configuration requires many equipment configurations and becomes expensive.
この発明は士Pのような問題点を解消するタメになされ
たもので、端末機器接続回路(4)と端末信号中継装置
■ルなくすことができる時分割多重通信装置を得ること
を目的とする。This invention was made to solve the problems mentioned above, and aims to provide a time division multiplex communication device that can eliminate the terminal device connection circuit (4) and the terminal signal relay device. .
この発明に係る時分割多重通信装置は、新たに分岐挿入
回路(7)を付加し、通信回線監視制御装置0と通信網
同期装置(至)と組合せて複数伝送路間の端末情報を送
受信データバス上で直接ディジタル分岐挿入したもので
ある。The time division multiplex communication device according to the present invention has a new add/drop circuit (7) added, and is combined with a communication line monitoring and control device 0 and a communication network synchronization device (to) to transmit and receive terminal information between multiple transmission paths. This is a digital drop/add directly on the bus.
この発明における、分岐挿入回路(7)は通信回線監視
制御値@0からの回線設定信号により複数装置間の分岐
挿入回線を指定し、また通信網同期装置(至)からの同
期信号により複数装置間の同期ルとることにより、送受
信データバス上で直接ディジタル分岐挿入が可能となる
。In this invention, the drop/add circuit (7) specifies a drop/add line between multiple devices by a line setting signal from a communication line monitoring control value @0, and also specifies a drop/add line between multiple devices by a synchronization signal from a communication network synchronizer (to). By providing synchronization between the data buses, direct digital branch/insertion can be performed on the transmit/receive data bus.
以下、この発明の一実施例を図について説明する。第1
図において(1)は伝送路Aに接続さrる装置、(2)
は伝送路Bに接続される装置、(3)はN話、データ、
画像等の各種端末機器、(4)は端末機器を装置(1)
、(2)に接続する端末接続回路、(5)は送信データ
バス、(6)は、受信データバス、(7)は分岐挿入回
路、(8)は伝送路A、Bへ装置(1)、(2)を接続
する伝送路接続回路、(9)は装置(1)、(21が正
常動作を行なうための々イミング発生回路、αOは、監
視制御回路、卸は通信回線監視制御装置、@は通信網同
期装置でゐり、また、分岐挿入回路(7)の詳細構成を
示す第2図において、(至)は自局受信データ用論回路
、α尋は分岐データ用RAM回路、Qlは損Wα4の書
き込み回路、αGは損因α4の読み出し回路、(ロ)は
IIき込み/読み出しの変位設定回路、QE9は自局送
信データ用ゲート回路、Q嗜は挿入デー々用ゲート回路
である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a device connected to transmission path A, (2)
is the device connected to transmission line B, (3) is N talk, data,
Various terminal devices such as images, (4) are terminal devices (1)
, (2) is a terminal connection circuit connected to, (5) is a transmission data bus, (6) is a reception data bus, (7) is a branch/add circuit, (8) is a device (1) connected to transmission paths A and B. , (2), (9) is a timing generation circuit for normal operation of the device (1), (21), αO is a supervisory control circuit, wholesale is a communication line supervisory control device, @ is a communication network synchronization device, and in FIG. is the write circuit for the loss Wα4, αG is the readout circuit for the loss cause α4, (b) is the displacement setting circuit for II writing/reading, QE9 is the gate circuit for own station transmission data, and Q is the gate circuit for the inserted data. be.
次に力作について説明する。伝送路Aからの受信データ
は装置(1)に接続さn、伝送路接続回路(8)で符号
変換、フレーム同期、クロック抽出、送受信データのフ
レーム位相同期を行ない、分岐挿入回路(7)に接続さ
れる。分岐挿入回路(7)では、自局の端末機器に接続
さnる受信デー々の必要ビットのみ、自局受信データ用
RAM回路(至)に書き込み、伝送路Bへ中継する受信
データのビットは、分岐データ用局(回路a4に書き込
む。RAM回路(至)、α→の書き込みアドレスの制御
は、塘α4の書き込み回路(至)、読み出しはRAM
(14の読み出し回路αGからの制御信号により行なう
。また書き込み回路(ト)と読み出し回路αGの位相差
(ビット数)は書き込み/読み出しの変位設定回路αη
により行なう。Next, I will explain the masterpiece. The received data from the transmission line A is connected to the device (1), and the transmission line connection circuit (8) performs code conversion, frame synchronization, clock extraction, and frame phase synchronization of the transmitted and received data, and then the data is sent to the add/drop circuit (7). Connected. In the branch/add circuit (7), only the necessary bits of the received data connected to the terminal equipment of the own station are written to the RAM circuit for the received data of the own station (to), and the bits of the received data to be relayed to the transmission path B are written. , Branch data station (Write to circuit a4. RAM circuit (to), α→ write address control is to α4 write circuit (to), read is to RAM circuit
(This is done by the control signal from the readout circuit αG of 14. Also, the phase difference (bit number) between the write circuit (g) and the readout circuit αG is determined by the write/read displacement setting circuit αη
This is done by
一方、自局端末捌器からの送信データは分岐挿入回路(
7)の自局送信デー々用ゲート回路(ト)、伝送路Bか
らの挿入データは、挿入データ用ゲート回路α呻で合成
さ1、伝送路接続回路(8)を経て伝送路Aへ送信され
る。On the other hand, the transmission data from the local terminal switcher is sent to the branch/add circuit (
7) The insertion data from the self-station transmission data gate circuit (g) and transmission line B are combined by the insertion data gate circuit α1 and sent to transmission line A via the transmission line connection circuit (8). be done.
送信データバス(5)、受信データバス(6)と端末機
器接続回路(4)及び端末機器(3)との接続は従来回
路の動作と同様であり、また、伝送路Bに関する動作も
上記伝送路Aの動作と同様である。The connections between the transmission data bus (5), the reception data bus (6), the terminal device connection circuit (4), and the terminal device (3) are the same as the operation of the conventional circuit, and the operation regarding the transmission path B is also the same as the transmission line B described above. The operation is similar to that of path A.
装@(υ、(2)の各分岐挿入回路(7)の分岐挿入デ
ータ入出力点を相互に接続すれば、送受信データバス上
と等価な状態で直接ディジタル分岐挿入が可能である。If the branch/insert data input/output points of each branch/insert circuit (7) of the system @(υ, (2)) are connected to each other, direct digital branch/insert can be performed in a state equivalent to that on the transmit/receive data bus.
具体的には、1台のa信回線監視制御装置■から受信デ
ータバス(6)上の々イムスロット番号でビットの分岐
開始、終了と、別の伝送路の送信データバス(5)への
変換するビットの変位量等の回線設定信号を装置(1)
、(2)に同時に指定し、また通信網同期袋gi(2)
から送受信データバスのフレーム位相同期がとれる同期
信号を装N(1)、(2)に同時に供給して装置! (
1)、(21間でフレーム位相同期をとることにより可
能となる。Specifically, the bit branching starts and ends at each time slot number on the reception data bus (6) from one A communication line monitoring and control device, and the bit branching to the transmission data bus (5) on another transmission path is performed. The device (1) sends line setting signals such as the amount of bit displacement to be converted.
, (2) at the same time, and the communication network synchronization bag gi(2)
A synchronization signal that can synchronize the frame phase of the transmitting and receiving data bus is simultaneously supplied to the device N (1) and (2) from the device! (
1), (This is possible by synchronizing the frame phase between 21.
なお、上記実施例では、伝送路A%Bのみで、 。In addition, in the above embodiment, only transmission path A%B.
分岐挿入口゛線は1ポートだけであったが、伝送路が2
以上の複数の場合でも、分岐挿入回路(7)の分岐挿入
ポートを2以上の複数にす1ば前記2方向の中継と同様
の効果を奏する。The branch insertion port had only one port, but there were two transmission lines.
Even in the above-mentioned case, if the add/drop ports of the add/drop circuit (7) are made into a plurality of two or more, the same effect as the two-way relay described above can be obtained.
また、本発明の回路による動作は、送受信データバスの
フレーム長が任意のものにも適用できる。Further, the operation by the circuit of the present invention can be applied to a transmission/reception data bus having an arbitrary frame length.
以上のように、この発明によIば1台の分岐挿入回路(
7)の追加により、複数個の、端末機器接続回路(4)
がなくなるような構成にしたので、装置が安価にでき、
また精度の高いものが得らする効果がある。As described above, according to the present invention, one branch/insertion circuit (
With the addition of 7), multiple terminal device connection circuits (4)
Since the structure is designed to eliminate the
In addition, there is an effect obtained by having high precision.
第1図はこの発明の一実施例による時分割多重通信装置
の回路構成、第2図は、この発明の分岐挿入回路の詳細
図、第8図は従来装置による回路摺成図を示す。
(1)は伝送路Aに接続さ釘る装置、(2)は伝送路B
に接続さする装置、(3)は端末機器、(4)は端末機
器接続回路、(5)は送信データバス、(6)は受信デ
ータバス、(7)は分岐挿入回路、(8)は伝送路接続
回路、(9)はタイミング発生回路、αOは監視制御回
路、卸は通信回線監視制御装置、@は通信網同期装置、
(至)は自局受信データ用脚回路、α4は分岐データ用
RAM回路、α→はRAMα→の書き込み回路、αGは
、RAM Q4の読み出し回路、αηは*S込み/読み
出しの変位設定回路、(至)は自局送信デー々用ゲート
回路、a9は挿入データ用ゲート回路、(イ)は端末信
号中継接続装置。
なお、図中、同一符号は、同一、又は相当部分を示す。FIG. 1 shows the circuit configuration of a time division multiplex communication device according to an embodiment of the present invention, FIG. 2 shows a detailed diagram of the add/drop circuit of the present invention, and FIG. 8 shows a circuit diagram of a conventional device. (1) is a nailing device connected to transmission line A, (2) is transmission line B
(3) is the terminal equipment, (4) is the terminal equipment connection circuit, (5) is the transmission data bus, (6) is the reception data bus, (7) is the branch/insertion circuit, (8) is the device to be connected to the Transmission line connection circuit, (9) is a timing generation circuit, αO is a monitoring control circuit, wholesale is a communication line monitoring and control device, @ is a communication network synchronization device,
(to) is a leg circuit for own station reception data, α4 is a RAM circuit for branch data, α→ is a write circuit for RAM α→, αG is a read circuit for RAM Q4, αη is a displacement setting circuit for *S loading/reading, (to) is a gate circuit for own station transmission data, a9 is a gate circuit for insertion data, and (a) is a terminal signal relay connection device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
時分割多重化方式にて伝送する通信装置において、1局
に1台設置する通信網同期装置からの同期信号基により
複数装置間の同期をとると共に、1局に1台設置する通
信回線監視制御装置からの回線設定信号により複数装置
間の分岐挿入回線を指定して複数の通信装置間で各種情
報を送受信バス上で直接ディジタル分岐挿入するように
したことを特徴とする時分割多重通信装置。In communication equipment that digitizes and transmits various information such as telephone calls, data, and images using a time-division multiplexing method, synchronization is achieved between multiple devices using a synchronization signal base from a communication network synchronizer installed at each station. At the same time, a line setting signal from a communication line monitoring and control device installed at each station specifies a branch/add line between multiple devices, and various information is directly digitally branched/inserted on the transmission/reception bus between multiple communication devices. A time division multiplex communication device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23061884A JPS61107837A (en) | 1984-10-30 | 1984-10-30 | Time division multiplex communication equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23061884A JPS61107837A (en) | 1984-10-30 | 1984-10-30 | Time division multiplex communication equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61107837A true JPS61107837A (en) | 1986-05-26 |
Family
ID=16910588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23061884A Pending JPS61107837A (en) | 1984-10-30 | 1984-10-30 | Time division multiplex communication equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61107837A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0367221A2 (en) * | 1988-10-31 | 1990-05-09 | Fujitsu Limited | Drop/insert multiplexer for data channel access units |
-
1984
- 1984-10-30 JP JP23061884A patent/JPS61107837A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0367221A2 (en) * | 1988-10-31 | 1990-05-09 | Fujitsu Limited | Drop/insert multiplexer for data channel access units |
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