JPS61105875A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61105875A
JPS61105875A JP22853384A JP22853384A JPS61105875A JP S61105875 A JPS61105875 A JP S61105875A JP 22853384 A JP22853384 A JP 22853384A JP 22853384 A JP22853384 A JP 22853384A JP S61105875 A JPS61105875 A JP S61105875A
Authority
JP
Japan
Prior art keywords
substrate
resist film
gold
resist
germanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22853384A
Other languages
Japanese (ja)
Inventor
Takeshi Nogami
毅 野上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22853384A priority Critical patent/JPS61105875A/en
Publication of JPS61105875A publication Critical patent/JPS61105875A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Abstract

PURPOSE:To enable to form correct wiring patterns by a method wherein a resist film, which is formed on the surface of the substrate, is removed in the interior of a closed and heated high-pressure container by a lift-off method. CONSTITUTION:Before a photo resist film 16is formed on a gallium arsenid semiconductor substrate 11, openings 14a and 14b are formed on insulating films 13. Subsequently, second openings 17a and 17b are formed and metal wiring layers 15 consisting of gold and germanium are formed by evaporation on the surface of the substrate 11. These are dipped in a resist dissolving liquid 19 in the interior of a closed container 18, which is heated by a heating coil L at high temperatures. The pressure in the interior of the closed container 18 rises by heating and is turned into a high pressure, the biling point of the resist dissolving liquid 19 rises, a reaction of the resist film 16 to dissolution is rapidly promoted and the gold-germanium layers 15 other than metal layers 15a and 15b, which are evaporated on the surface of the substrate 11, are securely removed along with the resist film 16. Accordingly, ohmic metal wirings 15a and 15b consisting of gold and germanium are correctly patterned corresponding to the prescribed wiring patterns. As a result, the highly reliable semiconductor device can be manufactured.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えば■S FET等の半導体素子の形成
された砒化ガリウム(GaAs )半導体基板の表面に
配線・母ターンを形成する際に用いられる半導体装置の
製造方法に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention is used for forming wiring/mother turns on the surface of a gallium arsenide (GaAs) semiconductor substrate on which semiconductor elements such as ■S FETs are formed. The present invention relates to a method for manufacturing a semiconductor device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に、シリコン基板を用いた半導体装置の場合、オー
ミックコンタクトの要求されるオーミックメタルはアル
ミニウムで良かった。これは、シリコン表面には準位が
あまり存在せず、メタルの種類を変えることでショット
キー障壁の高さ調整が容易であったこと、及び、不純物
イオンの打ち込み限界(固溶限界)が約1020m−2
と高く、トンネル効果によりオーミックコンタクトを得
ることが出来たことによるものである。
Generally, in the case of a semiconductor device using a silicon substrate, aluminum can be used as the ohmic metal that requires ohmic contact. This is because there are not many levels on the silicon surface, and the height of the Schottky barrier can be easily adjusted by changing the type of metal, and the implantation limit (solid solution limit) of impurity ions is approximately 1020m-2
This is due to the fact that ohmic contact can be obtained due to the tunnel effect.

一方、砒化ガリウムのような化合物半導体基板を用いて
半導体装置を製造する場合には、その表面準位がエネル
ギ伝導体の下端から3分の2のところに存在する禁止帯
中に設定されている為、上記シリコンの場合のように、
オーミックメタルを変えてもショットキー障壁の高さは
容易には変化せず、しかも上記固溶限界か10cln−
2程度であるのでトンネル効果を利用するのが難かしい
。このため金ダルマニウム(AuGe)を蒸着して合金
にすることによりオーミックコンタクトを得る手段が考
えられている。
On the other hand, when manufacturing a semiconductor device using a compound semiconductor substrate such as gallium arsenide, the surface level is set in the forbidden band that exists two-thirds from the bottom of the energy conductor. Therefore, as in the case of silicon,
Even if the ohmic metal is changed, the height of the Schottky barrier does not change easily.
Since it is about 2, it is difficult to utilize the tunnel effect. For this reason, a method of obtaining ohmic contact by depositing gold-dalmanium (AuGe) to form an alloy has been considered.

ここで、上記シリコン基板において用いられろアルミニ
ウム電極の場合には、周知の写真食刻法により形成され
た配線パターンをエツチングすることによりオーミック
電極が得られるが、一方、砒化、/j” IJウム基板
において用いられる金ゲルマニウム電極の場合には、上
記シリコンの場合と同様な方法でエツチングすると、次
のような問題点が生じる。
Here, in the case of the aluminum electrode used in the silicon substrate, an ohmic electrode can be obtained by etching a wiring pattern formed by a well-known photolithography method. In the case of gold germanium electrodes used in substrates, the following problems arise when etching is performed in the same manner as in the case of silicon.

(1)  金rルマニウム用の溶解液によりウェットエ
ツチングを施すと砒化ガリウム基板の表面を傷めてしま
う。
(1) If wet etching is performed using a gold-rumanium solution, the surface of the gallium arsenide substrate will be damaged.

(2)  金fルマニウムはRIE (ドライエツチン
グ)法では除去しにくい。
(2) Gold and rumanium are difficult to remove by RIE (dry etching).

(3)  ス・臂ツタリングによる場合、金ゲルマニウ
ムと保護膜そして砒化ガリウム基板との選択性が薄い。
(3) In the case of suttering, the selectivity between gold germanium, the protective film, and the gallium arsenide substrate is low.

この為、砒化ガリウム基板(GaAs )を用いた場合
には、アセトン等のエツチング強度の弱いレジスト剥離
液を常圧加熱して用いるリフトオフ法が使用されている
が、上記エツチング強度が弱い為に、容易に不要部分の
レジスト剥離を達成することができない。
For this reason, when using a gallium arsenide substrate (GaAs), a lift-off method is used in which a resist stripping solution with low etching strength, such as acetone, is heated under normal pressure. It is not possible to easily remove the resist from unnecessary parts.

そこで、上記リフトオフ法によるエツチング時に、超音
波を加えてレジスト剥離を推進させる手段または水スプ
レー処理による水圧によって上記剥離を推進させる手段
等が考えられているが、前者、超音波併用の場合にはG
aAs基板が割れる恐れがあり、また後者、水スプレー
併用の場合でも、その剥離効果は充分でない。したがっ
て、信頼性の高いエツチングが完了されるまでには、顕
微鈍による観察1点検等に多くの時間と人手が必要とな
り、砒化ガリウム基板による半導体装置量産化の妨げと
なっている。
Therefore, methods have been considered to apply ultrasonic waves to promote the resist peeling during etching using the lift-off method, or to promote the peeling using water pressure from water spray treatment. G
There is a risk that the aAs substrate may crack, and even if water spray is used in combination with the latter, the peeling effect is not sufficient. Therefore, until highly reliable etching is completed, a lot of time and manpower are required for one inspection using a blunt microscope, which is an obstacle to the mass production of semiconductor devices using gallium arsenide substrates.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような問題点に鑑みなされたもので、
リフトオフ法により配線ノ臂ターンを形成する際に、エ
ツチング完了までに観察2点検等を行なう必要なく、短
時間且つ信頼性の高いエツチングにより正確な配線パタ
ーンを形成することができるようになる半導体装置の製
造方法を提供することを目的とする。
This invention was made in view of the problems mentioned above.
To provide a semiconductor device that enables formation of an accurate wiring pattern through highly reliable etching in a short time without the need for two inspections before etching is completed when forming a wiring arm turn using a lift-off method. The purpose is to provide a manufacturing method for.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係る半導体装置の製造方法は、配線
・やターンに対応して開孔の形成されるレジスト膜及び
配線金属層の形成された化合物半導体基板を密閉容器内
で加熱される高温高圧のレノスト溶解液中に浸すことに
より、上記レジスト膜に対する溶解反応を強力に推進さ
せるようにしたものである。
That is, in the method for manufacturing a semiconductor device according to the present invention, a compound semiconductor substrate on which a resist film and a wiring metal layer are formed, in which openings are formed corresponding to wiring lines and turns, is heated in a closed container at high temperature and high pressure. By immersing it in the Lennost solution, the dissolution reaction of the resist film is strongly promoted.

〔発明の実施例〕[Embodiments of the invention]

以下図面によりこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図(A)乃至(D)及び第2図はその製造工程を示
すもので、まず同図(A)に示すように、化合物半導体
、例えば砒化ガリウム(GaAs )半導体基板1ノの
表面には、不純物拡散技術等により所定の回路パターン
に対応して高濃度層重及び低濃度MNを形成する。次に
、上記不純物拡散技術及びNからなる回路・母ターンの
ダート位置に対応してケゝ−ト電極12を形成し、この
ダート電極12を含む基板11表表面体に絶縁膜(Si
n2) 7 sを形成する。そして、この絶縁膜13に
は、所定の配線パターンに対応してホトエツチング技術
等により第1開孔(コンタクトホール)14a、14b
を形成し、との開孔14m、14bを含む基板11表面
には、第1図(B)に示すように、後述する金属配線層
15をリフトオフ法によりノ量ターニングする為のホト
レジスト膜16を形成する。
Figures 1 (A) to (D) and Figure 2 show the manufacturing process. First, as shown in Figure (A), the surface of a compound semiconductor, for example, gallium arsenide (GaAs) semiconductor substrate 1 is coated. In this method, a high concentration layer and a low concentration MN are formed in accordance with a predetermined circuit pattern using an impurity diffusion technique or the like. Next, a gate electrode 12 is formed corresponding to the dirt position of the circuit/mother turn made of N using the above impurity diffusion technique, and an insulating film (Si) is formed on the surface of the substrate 11 including the dirt electrode 12.
n2) form 7 s. Then, in this insulating film 13, first openings (contact holes) 14a, 14b are formed by photoetching or the like in correspondence with a predetermined wiring pattern.
A photoresist film 16 is formed on the surface of the substrate 11 including the openings 14m and 14b, as shown in FIG. Form.

次に、第1図(C)に示すように、このホトレジスト膜
16には、上記絶縁膜13の開孔14a。
Next, as shown in FIG. 1(C), the photoresist film 16 is provided with the openings 14a of the insulating film 13.

14bに続く配線・母ターンに対応した第2開孔(コン
タクトホール)17a、17bを形成し、この開孔17
a 、 17b域を含む基板11表面には、前述した金
ダルマニウム金属配線層(AuGa)15を蒸着形成す
る。そして、この金属層15を蒸着形成した砒化ガリウ
ム基板11を、例えば第2図に示すように、加熱コイル
Lにより高温加熱される密閉容器18内に貯められるア
セトン等のレジスト溶解液19中に浸す。
Second openings (contact holes) 17a and 17b corresponding to the wiring/mother turn following 14b are formed, and this opening 17
The aforementioned gold-dalmanium metal wiring layer (AuGa) 15 is formed by vapor deposition on the surface of the substrate 11 including regions a and 17b. Then, the gallium arsenide substrate 11 on which the metal layer 15 has been formed by vapor deposition is immersed in a resist solution 19 such as acetone stored in a closed container 18 heated to a high temperature by a heating coil L, for example, as shown in FIG. .

この場合、上記密閉容器18内の圧力は、加熱により上
昇し高圧となる。この為、上記レジスト溶解液(アセト
ン)19の沸点は大気圧(1atm )下では563℃
であるが、高圧下でのその沸点は下記に示すように上昇
する。
In this case, the pressure inside the closed container 18 increases due to heating and becomes high pressure. Therefore, the boiling point of the resist solution (acetone) 19 is 563°C under atmospheric pressure (1 atm).
However, its boiling point under high pressure increases as shown below.

一般に、化学反応速度を表わす速度定数には、え−い、
−Ea/RT と表わされる。ここで、Tは絶対温度、Eaは活性化エ
ネルギー、Rは気体定数、Aは定数である。これらの値
はレジストの種類及び溶解液により異なるが、上記反応
速度は、通常、溶解液温度が10℃上昇する毎に2〜3
倍速くなる。
In general, the rate constant that represents the rate of a chemical reaction is
-Ea/RT. Here, T is the absolute temperature, Ea is the activation energy, R is the gas constant, and A is the constant. Although these values vary depending on the type of resist and the solution, the above reaction rate usually increases by 2 to 3 for every 10°C increase in the temperature of the solution.
It's twice as fast.

これにより、レジスト膜16の溶解反応は強烈且つ迅速
に推進されるようになり、第1図(ロ)に示すように、
基板11表面に蒸着された金属層15h、15b以外の
金ダルマニウム層15は、レジスト膜16と共に確実に
除去されるようになる。ここで、上記金ゲルマニウム(
AuGe )層15のノリーニングを、例えばl Oa
tm 。
As a result, the dissolution reaction of the resist film 16 is promoted intensely and quickly, and as shown in FIG. 1(b),
The gold-dalmanium layer 15 other than the metal layers 15h and 15b deposited on the surface of the substrate 11 is reliably removed together with the resist film 16. Here, the above gold germanium (
For example, lOa
tm.

144.5℃の条件下で実施すると、上記レジスト膜1
6は数分で確実に剥離され、リフトオフ法によるエツチ
ングは100俤達成されるようになる。したがって、所
定の配線ノfターンに対応して金ゲルマニウム(AuG
e)からなるオーミックメタル配線15m、15bは正
確にノ4ターニングされるようになり、信頼性の高い半
導体装置の製造が可能になる。
When carried out under the condition of 144.5°C, the above resist film 1
6 can be reliably peeled off in a few minutes, and etching of 100 layers can be achieved by the lift-off method. Therefore, gold germanium (AuG) is
The ohmic metal wirings 15m and 15b consisting of e) can be accurately turned, making it possible to manufacture a highly reliable semiconductor device.

尚、上記実施例ではレジスト溶解液として、アセトンを
使用する場合について述べたが、例えばメチル、エチル
、ケトン等の溶解液を使用しても同様の効果を得ること
ができる。
In the above embodiment, the case where acetone is used as the resist dissolving solution has been described, but the same effect can be obtained by using a dissolving solution such as methyl, ethyl, ketone, etc.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、化合物半導体基板の表
面にリフトオフ法により所定の配線ノ4ターンをパター
ニングする際に、密閉加熱容器内の高温高圧の溶解液に
よりホトレジスト膜を除去するようにしたので、レジス
ト膜に対する溶解反応を強力に推進させることができ、
短時間且つ確実なノ’?ターニングにより信頼性の高い
半導体装置を製造できる。これにより、化合物半導体基
板を用いた半導体装置の量産性を向上することができる
As described above, according to the present invention, when patterning four turns of predetermined wiring on the surface of a compound semiconductor substrate by the lift-off method, the photoresist film is removed using a high-temperature, high-pressure solution in a sealed heating container. Therefore, the dissolution reaction for the resist film can be strongly promoted.
A short and reliable no'? Turning allows manufacturing of highly reliable semiconductor devices. Thereby, mass productivity of semiconductor devices using compound semiconductor substrates can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)乃至υ)はこの発明の一実施例に係る半導
体装置の製造方法をその製造工程順に示す断面構成図、
第2図は上記製造工程における高圧リフトオフによるエ
ツチング過程を示す図である。 11・・・砒化ガリウム半導体基板、15・・・配線金
属層、16・・・ホトレゾスト膜、17a、Ilb・・
・開孔、18・・・密閉容器、19・・レジスト溶解液
、L・・・加熱コイル。
1(A) to υ) are cross-sectional configuration diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps;
FIG. 2 is a diagram showing the etching process by high-pressure lift-off in the above manufacturing process. 11... Gallium arsenide semiconductor substrate, 15... Wiring metal layer, 16... Photoresist film, 17a, Ilb...
・Open hole, 18... Sealed container, 19... Resist solution, L... Heating coil.

Claims (1)

【特許請求の範囲】[Claims]  化合物半導体基板の表面に配線パターンに対応して開
孔の形成されるレジスト膜を形成する手段と、このレジ
スト膜の形成された半導体基板の表面に配線金属層を形
成する手段と、この後上記基板表面に形成したレジスト
膜を密閉加熱高圧容器内にてリフトオフ法により除去す
る手段とを具備したことを特徴とする半導体装置の製造
方法。
means for forming a resist film in which openings are formed corresponding to a wiring pattern on the surface of a compound semiconductor substrate; means for forming a wiring metal layer on the surface of the semiconductor substrate on which the resist film is formed; 1. A method for manufacturing a semiconductor device, comprising means for removing a resist film formed on a surface of a substrate by a lift-off method in a sealed heated high-pressure container.
JP22853384A 1984-10-30 1984-10-30 Manufacture of semiconductor device Pending JPS61105875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22853384A JPS61105875A (en) 1984-10-30 1984-10-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22853384A JPS61105875A (en) 1984-10-30 1984-10-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61105875A true JPS61105875A (en) 1986-05-23

Family

ID=16877894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22853384A Pending JPS61105875A (en) 1984-10-30 1984-10-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61105875A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007083791A1 (en) * 2006-01-23 2007-07-26 National Institute Of Advanced Industrial Science And Technology Method of liftoff working and liftoff working apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007083791A1 (en) * 2006-01-23 2007-07-26 National Institute Of Advanced Industrial Science And Technology Method of liftoff working and liftoff working apparatus
JP2007221096A (en) * 2006-01-23 2007-08-30 Ryusyo Industrial Co Ltd Lift-off processing method and lift-off processing apparatus

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