JPS59161074A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To control the size of minute gate length precisely, and to obtain an excellent Schottky junction surface, which is not affected by the damage of a semiconductor surface at all, by providing a process in which an insulating film formed on a substrate is bored with high accuracy, a process shaping a metal reacting with the substrate at a low temperature and a process reacting the metal in depth depper than a damaged layer. CONSTITUTION:<28>Si<+> ions are implanted to a semi-insulating GaAs substrate 1, an implanted ion layer is activated through heat treatment, and an N conductive layer 2 is formed. An SiO2 film 3 is deposited, and source and drain electrodes 4, 5 are shaped. The SiO2 film in gate sections is bored through etching. Pt is evaporated on the whole surface under vacuum while leaving a photo-resist 6 as it is, and a gete electride 9 is formed. All damaged layers in the vicinity of the surface of GaAs react with Pt through heat treatment to form compounds 10, and the compounds and a section, which is not affected by a damage at all, of the inside of a GaAs crystal form an excellent Schottky junction surface 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a field effect transistor J ('MESFET) having a gate Schottky junction.

[Prior art and its problems]

In general, GaAs MESFETs are widely used as individual elements constituting high frequency amplifiers, oscillators, and the like.

Moreover, recently, it is playing an important role as a basic element of GaAs IC. In both of these applications, a major reason is the rapid switching time of the single FET, which is due to the fact that the electron mobility of GaAs is several times greater than that of St.

The relationship between the switching time tpd of a MESFET and its gate length Lg is tpd x tg. Therefore, the switching time of the transistor is
- In order to speed up the switching time, it is necessary to reduce the gate length tgk, and even now gate lengths of about 1 μm have been obtained. Furthermore, it is expected that in the future, with the development of photolithography technology, submicron gates will become possible.

When forming such a minute gate electrode, a lift-off method is used, in which an insulating film is formed on the semiconductor substrate, the gate portion is opened, and unnecessary metal is removed using a photoresist or the like as a mask; Alternatively, a method is generally used in which the photoresist is removed once after the gate portion has been removed, metal is deposited on the entire surface, and then buttering is performed again to etch and remove unnecessary metal. These methods require 1 step after forming a metal film directly on a semiconductor substrate.
Unnecessary gold Rf: Compared to the method of etching and removing, this method has the following advantages: it is easier to control the minute gate length, that is, the size of the metal-semiconductor junction surface, and metal etching does not particularly damage the semiconductor surface.

However, when the gate length becomes extremely narrow, such as 1 μm or less, when a conventional aqueous solution etching method or a normal plasma etching method is used to etch the insulating film, the dimension due to side etching becomes smaller. conversion occurs, making precise control of fine gate lengths extremely difficult.

For this reason, for example, reactive ion etching (R.

Anisotropic etching with small dimensional conversion differences, such as the 1, E, ) method, is required. However, in anisotropic etching, since the particles contributing to etching have relatively large energy, damage to the semiconductor surface is inevitable, and as a result, the Schottky junction is adversely affected. This damage is generally said to be remedied by high-temperature heat treatment at 450°C or higher, but in the case of compound semiconductors such as GaAs, high-temperature heat treatment tends to cause deterioration of the substrate due to evaporation of the substrate elements. The above-mentioned high-temperature heat treatment requires complicated and dangerous steps.

Moreover, especially when using the lift-off method, it is difficult to perform such heat treatment before lift-off.

For this reason, anisotropic etching cannot be used to open the gate portion of the insulating film.

[Purpose of the invention]

The present invention was developed in view of the above-mentioned drawbacks, and it is possible to precisely control the gate length using anisotropy and etching, and to create a good Schottky that is completely unaffected by damage on the surface of a single conductor. The present invention provides a method for obtaining a bonded surface.

[Summary of the invention]

pt and Pd are relatively low temperature (300-40
0°C) to form intermetallic compounds such as PtAs (and PdA8), but these compounds also form good Schottky junctions with GaAs.
Proceeds toward the inside of the aAs crystal. Taking the Pti example, PT with a thickness of 1000A reacts almost completely by heat treatment at 380°C for 30 minutes, and a compound with a thickness of about 200OA reacts with GaA.
It is formed inside the crystal of No.3.

In addition, damage caused by anisotropic etching such as RIE,
Type of gas used for etching, gas pressure, gas flow rate,
Although it varies depending on high-frequency power, etc., in the commonly used CF4 gas-based R and IJ, the damage layer is formed at a depth of about 300 to 500 degrees from the crystal surface.

Therefore, R', 1. After opening the gate area by anisotropic etching such as E, if Pt or Pd i is allowed to react deeper than this damaged layer, the damaged layer will react with the metal and completely disappear, leaving the GaAs layer intact. A good Schottky junction without any damage effects can be obtained inside the crystal.

〔Effect of the invention〕

According to the present invention, by using anisotropic etching such as RIE! +, MESFET gate length can be precisely controlled to 1 μm or even submicron, and furthermore, a good Schottky junction without any damage can be used without requiring complicated processes.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4.

28Si ions on semi-insulating GaA3 substrate (1)
After implantation at a 100 KV dose of 3 Ocm 2 , heat treatment is performed at 850° C. for 15 minutes in an arsenic atmosphere to activate the implanted ion layer and form an n-type conductive layer (2). After this, the 5i02 film (3) was heated to about 300O by low-temperature CVD method.
Then, source and drain electrodes (4) and +5) made of AuGe ohmic metal are formed using conventional photolithography and lift-off methods. After that, photolithography of the gate part is performed, and the parallel plate type R,1,
Using the E device, the sio layer and film at the gate portion are etched and opened.

At this time, a mixed gas of CFa and H2 was used as the etching gas, and the flow rates were CF420 sec and CF420 sec, respectively.
It was H210SCCM. The total pressure of etching gas is 5
-Torr, and the high frequency power density is 0.3 W/crA. The etching speed at this time is 525 Sin.
A/rn i n , GaAs is 50 A/111i
n or less, a selectivity ratio of SiO2 to GaAs of 10 or more has been obtained. Etching time is 6 minutes, 5i0
The overetching is by a factor of 5 for the 2 film 3000A, but this is because it is taken into consideration that the in-plane thickness distribution of the 5io2 film (3) is usually several percent.

In fact, it was confirmed that the variation in opening size within the 2φ GaAs crystal plane was extremely small when etching was carried out under this 5% overetching condition. In fact, while the opening of the photoresist before etching was 1 μh1, the opening (7) of 5102M after etching was 1.02 μm, and the pattern conversion difference was about 2% at most, 1ζ. By the way, due to this overetching condition, GaAs is 1
Although it is etched by 0 to 20A, it is almost negligible because the thickness of the n-type conductive layer (2) is about 200OA. However, a damaged layer (8) of approximately 50 OA is formed under the opening (7) (FIG. 1).

After this, leave the photoresist (6) and remove Pt 70.
A gate electrode (9) was formed by vacuum deposition on the entire surface with a thickness of 0 Å and a lift-off method (FIG. 2).

When the Schottky characteristics between the gate electrode (9) and the source electrode (4) are measured in this state, the n value and barrier potential height φB, which are indicators of the quality of the Schottky junction, are n = 1.64 + φB, respectively. = 0.64, compared to the value when the gate opening was performed by wet etching with an aqueous solution containing 30% ammonium fluoride and 6% hydrogen fluoride, n = 1.25, and φB = 0.82. , has gotten very bad. This is R,I. This all suggests that the damage to the GaAs surface during E is significant.

In addition, the time during which the GaAs surface is directly irradiated with plasma varies depending on the in-plane thickness distribution of the 5i02 film.
The amount of damage received by s varies depending on the location, and the variation in the n value is also large.

Thereafter, heat treatment was performed at 380° C. for 5 minutes and 15 minutes in an N2 atmosphere, and the changes in the n value and φB are shown in FIGS. 3 and 4, respectively. In the figure, the openings in the gate portion shown by white circles and solid lines are those etched by RIE, and the ones shown by black circles and broken lines are those made by wet etching. Figures 3 and 4
As can be seen from the figure, in the state immediately after p t 'i bonding, the gate section opened by RIE is strongly affected by damage to the GaAs surface, and although it is a good Schottky junction. However, after heat treatment at 380° C. for 5 minutes, the value is almost the same as that obtained by wet etching, and a very good Schottky junction is formed. Furthermore, the variation in the n value due to the difference in the amount of damage received is also sufficiently small.

In addition, our experiments have shown that in heat treatment at 380° C. for 5 minutes, 300A out of 7ooA of pt reacts with GaAs, forming a compound of about 600X inside the GaAs crystal.

From these reasons, heat treatment at 380°C for 5 minutes9, G
All the damaged layers near the aAs surface react with pt to form a compound arue, and this compound and the GaAs
It can be seen that the portion that is completely unaffected by damage inside the crystal forms a good Schottky bonding surface (11) (FIG. 5).

Further, the value of the thickness of the damaged layer of about 5ooX described above is also supported by this experimental result.

It was also confirmed that this value does not depend much on etching time.

After this, the reaction gold of Pt and GaAs was further advanced to substantially reduce the thickness of the n-type conductive layer (2), and an enhancement type MESFET was fabricated, which was no different from that made using the conventional wet etching method. F without
ET characteristics were obtained. Furthermore, the gate length is 1 μm for a mask pattern of 1 μm.
．． While there was a tendency to spread to 2 μm ± 0.2 μm,
In this example, the thickness of 1.0 μm±0.02 μm was obtained with extremely high precision and good uniformity.

As described above, in the MESFET manufacturing method according to the present invention, since the damaged layer is removed by reaction with the gate metal such as PT, the thickness of the conductive layer at the start of the process is increased in consideration of the thickness of the damaged layer. Needless to say, it is necessary to keep it. In addition, enhancement type ME8FET
In the case of R
It is desirable that the etching of the GaAs surface by IE be kept below <20 A as in this embodiment. We have confirmed that under these conditions, an enhancement-type MESFET with almost no defects can be obtained across the entire surface of the γφ wafer.

[Embodiments of the invention]

In the above embodiment, the case where the gate length is 1 μm has been described, but from the viewpoint of high precision and high uniformity, the case where the gate length is submicron can also be satisfactorily supported. In addition, gate metals are not limited to PT.
For example, any material such as Pd that can react with GaAs at low temperatures and that the reaction product forms a good Kasjotky junction with GaAs may be used.

The insulating film is not limited to 5iO1, but may also be made of, for example, Si3N4. As for the etching method, any etching method that provides anisotropy can be used as long as the etching rate of the substrate is not extremely high or that does not cause very deep damage to the substrate. Furthermore, the method for forming the n-type conductive layer is not limited to the above-mentioned ion implantation method, and a well-known eviaxial growth method may be used.

Furthermore, the present invention can be applied to manufacturing a 5FET using not only GaAs but also other semiconductors such as St, by selecting the etching method and metal for the gate electrode.

[Brief explanation of drawings]

1, 2 and 5 are cross-sectional views for explaining the method of manufacturing a field effect transistor of the present invention, and FIGS. 3 and 4 show the Schottky characteristic n value and barrier potential height, respectively. It is a graph showing changes in φB depending on heat treatment time. ]... Semi-insulating GaA s substrate 2... N-type conductive layer 3... sio, film 4...
- Source electrode 5...Drain electrode 6...Photoresist 7...Gate opening 8...Damaged layer 9...Metal for gate electrode 10...Metal compound for gate electrode 11...Shot Key joint agent Patent attorney Kensuke Chika (and 1 other person) 1st
Figure 8: Karukan Pen (interference L + piercing 15i!rM) →

Claims (1)

[Claims] A process of accurately opening an insulating film formed on a semiconductor substrate using an anisotropic etching method (a process of forming a gate electrode with a metal that reacts with the semiconductor substrate at low temperatures, and a process of forming a metal that reacts with the semiconductor substrate at low temperatures through low-temperature heat treatment). 1. A method for manufacturing a field effect transistor, comprising the step of causing a reaction with a substrate deeper than a damaged layer caused by anisotropic etching.