JPH04279035A - Manufacture of field-effect-transistor - Google Patents

Abstract

PURPOSE:To provide for a manufacturing method with a low thermal resistance and less scattering in manufacture of a field-effect-transistor for power amplifier. CONSTITUTION:After creating an operation portion of a field-effect-transistor on an etching-prevention layer, a semiconductor substrate is selectively eliminated by etching and a penetration hole is provided at a thin semiconductor portion on the etching-prevention layer. Thickness of the semiconductor portion determining thermal resistance can be made thin uniformly, the semiconductor substrate is selectively eliminated by etching, and a penetration hole is provided at a thin semiconductor portion on the etching-prevention layer. A thickness of the semiconductor portion determining thermal resistance can uniformly be made thin and a via hole with a thinner aperture can be provided.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for manufacturing a field effect transistor, particularly a field effect transistor (hereinafter referred to as FET) using a compound semiconductor that performs power amplification.

[Conventional technology]

FETs used for amplifying high power require a gate electrode width of several millimeters, which is much longer than the distance between the drain and source electrodes. For this reason, the drain
A comb-shaped structure is used, which is a gate electrode structure in which a plurality of gate electrode fingers provided in parallel between source electrodes are connected. In the comb-shaped structure, in order to form multilayer wiring, it is necessary to form two-layer wiring in the air (air bridge), electrodes that penetrate the substrate (via holes), and the like.

[0003]FETs that perform power amplification are required to emit as heat the same amount of power as the output power. In particular, compound semiconductors such as GaAs have low thermal conductivity. For this reason, electrodes constituting a field effect transistor are formed on the surface of a semiconductor substrate with a thickness of 200 to 500 μm, and then,
Mechanically polish the back side of the semiconductor substrate to 30 to 100 μm
The thickness is designed to reduce thermal resistance.

The manufacturing process of FET according to such a conventional technique will be explained below with reference to FIG.

A buffer layer 3 and an active layer 4 are epitaxially grown on a substrate 1 made of a semi-insulating GaAs semiconductor single crystal. An electrode 5 constituting a field effect transistor is fabricated on the active layer 4. A wax 6 that serves both as an element protector and an adhesive is applied onto the active layer 4 and attached to a support 7. (Figure 2
(a))

Next, the back surface of the substrate 1 is mechanically polished until the thickness of the substrate 1 is 60 μm. Thereafter, chemical polishing is performed until the substrate 1 has a thickness of 30 μm. A resist pattern 9 having a predetermined opening is formed by photolithography on the back surface of the substrate 1.
' to form. Using resist pattern 9' as a mask,
Via hole 8 is formed using reactive dry etching using Cl2 gas. (Figure 2(b))

After removing the resist pattern 9', photolithography is performed on the back surface of the substrate 1 to form a resist pattern 9 for element isolation. Metal layer (Ti/Au
) 10 is formed on the entire surface to form a through electrode in the via hole. (FIG. 2(c)) Metal layer (Ti/Au) corresponding to resist pattern 9 by lift-off method
Remove 10. Wet etching is performed using the metal layer (Ti/Au) 10 as a mask to isolate the elements. Finally, the field effect transistor is peeled off from the support 7.

[Problem to be solved by the invention]

In conventional FET manufacturing methods, processing using abrasive grains causes problems such as the surface flatness being determined by the size of the abrasive grains themselves and the formation of a process-affected layer. Further, in processing by etching, there are problems such as uniformity of etching and unevenness on the substrate surface at the start of etching remaining as it is at the end of etching. For these reasons, it is difficult to reduce the thickness of a semiconductor substrate from 200 to 500 μm to 1 to 10 μm and to achieve the desired substrate thickness with good reproducibility.
It has not been possible to reduce the thickness of a semiconductor substrate of 0 mm or more to 30 μm or less.

That is, the flatness of the surface is determined by the size of the abrasive grain itself, and the semiconductor substrate cannot be made thinner than this flatness. Furthermore, since a process-affected layer is formed on the back surface of the semiconductor substrate, it is necessary to leave a certain amount of thickness in order not to affect the characteristics of the field effect transistor.

When creating a through hole in such a semiconductor substrate, due to problems in polishing technology, (1) Since the substrate 1 after polishing has a thickness of about 30 μm, a through hole (through hole) of 1 to 10 μm is required. difficult to form. (2) Variations in the thickness of the semiconductor substrate due to the back polishing process cause variations in the thermal resistance of field effect transistors. Such problems arise.

The present invention solves the above-mentioned drawbacks, and an object of the present invention is to polish a semiconductor substrate from 1 to 1 by a back polishing process.
It is an object of the present invention to provide a method for manufacturing an FET having a through electrode having a diameter of 1 to 10 μm by reducing the thickness to 0 μm. Furthermore, by improving the controllability of the substrate thickness between substrates and within the plane of the substrates, variations in thermal resistance of each FET can be reduced.

[Means to solve the problem]

The method for manufacturing a field effect transistor according to the present invention includes a first step of forming an etching stopper layer and a semiconductor layer on one main surface of a substrate, and forming a gate electrode, a source electrode, and a drain electrode on the semiconductor layer. a second step of forming a semiconductor layer; a third step of etching the substrate using an etching means capable of obtaining a sufficient selectivity between the substrate and the etching stopper layer to expose the etching stopper layer; and a third step of etching the substrate to expose the etching stopper layer; The present invention is characterized in that a fourth step of forming a hole and a fifth step of connecting both main surfaces of the substrate with a metal layer through the through hole are sequentially performed.

[Effect]

After forming the active part of the field effect transistor on the etching stop layer, the semiconductor substrate is selectively etched away, so that the thickness of the semiconductor part of the field effect transistor, which determines the thermal resistance, is made uniform. Can be made thinner. At the same time, since a through hole is provided in this thin semiconductor portion, a hole with a smaller diameter can be provided.

[0014]

EXAMPLE The manufacturing process of an FET which is an example of the present invention will be explained below with reference to FIGS. 1(a) to 1(c).

As shown in FIG. 1(a), semi-insulating Ga
Substrate 1 made of As semiconductor single crystal (thickness: 400 μm,
Al0.29Ga0.71 on the surface of diameter: 50mm)
Etching stop layer 2 made of As semiconductor layer (thickness: 1μ
m), a buffer layer 3 made of a high resistance GaAs semiconductor;
(thickness: 10 μm) and an active layer 4 (thickness: 0.15 μm) made of GaAs semiconductor containing silicon as an N-type impurity.
μm) are sequentially epitaxially grown using an MBE (molecular beam epitaxial) device. Al0.29Ga0.
Etching stop layer 2 made of 71As semiconductor layer is made of Ga
It has a composition that can be lattice matched with an As semiconductor. If necessary, high resistance and/or low resistance GaA is formed on the active layer 4.
s semiconductor layer is grown at the same time.

An electrode 5 constituting an FET is formed on the active layer 4. This electrode 5 is composed of a source electrode/drain electrode that forms an ohmic contact with the active layer 4 and a gate electrode that forms a Schottky junction. Usually, several tens to several thousand electrodes 5 constituting FETs are formed on the same substrate 1.

Next, as shown in FIG. 1(b), the active layer 4
The surface side of the substrate 1 on which the electrodes 5 are provided is covered with a wax 6 that also protects the elements, making it flat and having sufficient rigidity.
Fixed to. Here, a glass plate whose area is wider than the surface of the substrate 1 and is polished flat is used as the support 7. Particle size 2
The back surface of the substrate 1 is mechanically polished using 0 μm abrasive grains, so that the thickness of the substrate 1 is 60 μm. Next, the substrate 1 is chemically polished until its thickness becomes 30 μm. The abrasive (
Etching solution): H2SO4:H2O2:H2
A mixed solution of O=10:1:1 is used. As a result, the unevenness on the back surface of the substrate 1 is within 20 μm.

Subsequently, selective etching is performed under the condition that only the substrate 1 made of GaAs is etched and the etching stopper layer 2 made of Al0.29Ga0.71As is not etched. This selective etching is based on SF6:S
Using a mixed gas of iCl4=1:50, reaction pressure: 50
mTorr, RF power: 100W, substrate temperature: 40℃
This is done by reactive ion etching for 300 minutes. Selectivity ratio (etching rate ratio of GaAs/AlGaAs)
is about 100, so when the substrate 1 is completely removed and the etching stopper layer 2 is exposed, the unevenness on the back surface of the substrate 1 caused by the previous process is 0.2 μm on the surface of the etching stopper layer 2. The unevenness is reduced to within 300 degrees and becomes sufficiently smooth. The etching stop layer 2 is made of KI:I2:H2O
=113:65:100 etching solution. This etching solution selectively removes AlGaAs and does not etch the buffer layer 3 made of GaAs.

As shown in FIG. 1(c), the buffer layer 3
Photolithography is performed on the top to form a resist pattern (
(not shown). Using this as a mask, via hole 8 is formed using reactive dry etching using Cl2 gas. Note that it is also possible to form a wiring layer connected to the electrode 5 on the active layer 4 in advance, and form the via hole 8 at a position connected to the wiring layer.

Photolithography is performed again to form a resist pattern 9. This resist pattern 9 is provided corresponding to a region separating a plurality of FETs formed on the substrate 1. After that, a metal layer (Ti/
Au) 10 is formed on the entire surface. By removing the resist pattern 9 using a lift-off method, unnecessary portions of the metal layer (Ti/Au) 10 are removed. NH4OH:H2O2
:H2O=2:1:100 solution was used to form a metal layer (T
The buffer layer 3 and active layer 4 are etched for 15 minutes using i/Au) 10 as a mask. Thereby, a plurality of FETs formed on the same substrate 1 can be separated. Finally, the FET is peeled off from the support 7.

The thickness of the FET (thickness of the buffer layer 3 and active layer 4) produced by the above steps is 10.8 to 11.
．． The thickness is 0 μm, and the variation in thickness is 0.2 μm or less. The thickness, which determines the thermal resistance, can be arbitrarily determined by setting the thicknesses of the buffer layer 3 and the active layer 4 during epitaxial growth. Therefore, thermal resistance can be easily reduced. Moreover, the unevenness on the surface is reduced in the selective etching process, and the uniformity of the back polishing process is improved, so that the uniformity of thermal resistance can be improved.

Furthermore, since the thickness of the FET can be reduced, the diameter of the through hole can also be made to be approximately the same as the thickness. Therefore, electrodes such as the source electrode can be miniaturized, the FET can be made smaller, and it can also be used in higher frequency microwaves.

In the above embodiments, the case where AlGaAs was used as the etching stop layer was explained, but G
aAs, AlGaAs, AlAs, Ge, ZnSe, etc.
It is also possible to adapt to any combination of structures and compositions that allow growth of the active layer.

[0024]

As explained above, the method for manufacturing a field effect transistor according to the present invention includes the first step of forming an etching stopper layer and a semiconductor layer on one main surface of a substrate, and forming a gate on the semiconductor layer. a second step of forming an electrode, a source electrode, and a drain electrode; a third step of etching the substrate by an etching means that can obtain a sufficient selectivity between the substrate and the etching stopper layer to expose the etching stopper layer; , a fourth step of forming a through hole penetrating the semiconductor layer, and a fifth step of connecting both main surfaces of the substrate with a metal layer through the through hole are sequentially performed. It is something.

[0025] Therefore, in a simple process and easily
A field effect transistor with a through electrode of 10 μm can be manufactured. Furthermore, since the distance from the surface of the field effect transistor to the backside metal film is uniform, the uniformity of thermal resistance is improved and reliability is improved.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram for explaining the manufacturing process of a field effect transistor according to the present invention.

FIG. 2 is a conceptual diagram for explaining the manufacturing process of a field effect transistor according to the prior art.

[Explanation of symbols]

1...Substrate,
2... Etching stop layer, 3... Buffer layer, 4...
active layer, 5... electrode,
6...Wax, 7...Support
8...
Via hole (through hole), 9... resist pattern,
10...Metal layer (Ti/Au
).

Claims (1)

[Claims] 1. A first step of forming an etching stop layer and a semiconductor layer on one main surface of a substrate; a second step of forming a gate electrode, a source electrode, and a drain electrode on the semiconductor layer; a third step of etching the substrate using an etching means capable of obtaining a sufficient selectivity between the etching stopper layer and the etching stopper layer, and exposing the etching stopper layer; a fourth step of forming a through hole penetrating the semiconductor layer; and a fifth step of connecting both main surfaces of the substrate with a metal layer through the through hole.