JPH0465835A - Manufacturing of field effect transistor - Google Patents

Abstract

PURPOSE:To uniformly make small the thickness of a semiconductor of a field effect transistor to decide heat resistance by removing the etching selectively on a semiconductor substrate, after forming a moving portion of the field effect transistor on an etching block layer. CONSTITUTION:Epitaxial growth is consecutively applied for an etching block layer 2, a buffer layer 3, and an activating layer 3, on the surface of a substrate 1 composed of semi-insulating GaAs semiconductor single crystals. The etching block layer 2 is composed of Al0.29Ga0.71As semiconductors. The buffer layer 3 is composed of highly-resistant GaAs semiconductors. The activating layer 3 is composed of GaAs semiconductors containing silicon of N-type impurities. On an activating layer 3', an electrode 4 to constitute a field effect transistor is formed. Then, the back side of the substrate 1 is chemically polished until its thickness get to 30mum. Next, only the substrate 1 is etched, selective etching is applied to the etching block layer 2 under the conditions of no etching. As a result, when the substrate 1 is completely removed, and the etching block layer 2 is exposed, level difference on the back side of the substrate 1 is reduced, and is made fully flat.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a method for manufacturing a field effect transistor, particularly a field effect transistor using a compound semiconductor that performs large power amplification.

[Prior Art] A field effect transistor that performs power amplification is required to emit power as heat as the output power. In particular, compound semiconductors such as GaAs have low thermal conductivity. For this purpose, electrodes constituting a field effect transistor are formed on the surface of a semiconductor substrate with a thickness of 200 to 5.0 μm, and then the back surface of the semiconductor substrate is mechanically polished to a thickness of 30 to 100 μm to reduce thermal resistance. ing.

[Problem to be solved by the invention]

However, in conventional mechanical polishing using abrasive grains,
It has not been possible to reduce the thickness of a semiconductor substrate having a diameter of 50 mm or more to 30 μm or less.

That is, the flatness of the surface is determined by the size of the abrasive grain itself, and the semiconductor substrate cannot be made thinner than this flatness. Furthermore, since a process-affected layer is formed on the back surface of the semiconductor substrate, it is necessary to leave a certain amount of thickness in order not to affect the characteristics of the field effect transistor.

In order to remove the influence of such a process-affected layer, etching may be performed.

In this case, although it is possible to remove the influence of the process-affected layer by 7 degrees, the flatness deteriorates more than when machining, and it is therefore essential that the thickness of the semiconductor substrate be at least a certain level. Furthermore, the thickness within the plane of the semiconductor substrate becomes non-uniform, causing variations in thermal resistance between elements.

For these reasons, it has been difficult to make the semiconductor substrate have a thickness of 30 μm or less.

The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide a method for manufacturing a field effect transistor, which allows a semiconductor substrate to be made thin to about 1 to 10 μm, and has less variation in thermal resistance between elements. It provides:

[Means and Effects for Solving the Problems 1] The method for manufacturing a field effect transistor according to the present invention includes a first step of forming an etching stopper layer on one main surface of a semiconductor substrate; forming a semiconductor layer on the etching stopper layer; a second step of forming;
a third step of forming a gate electrode, a source electrode, and a drain electrode on the semiconductor layer; a fourth step of physically and/or chemically etching the other main surface of the semiconductor substrate; and etching the semiconductor substrate. a fifth step of etching the semiconductor substrate using an etching means that can obtain a sufficient etching selectivity with respect to the etching stopper layer, and exposing the etching stopper layer; and at least one metal layer on the exposed etching stopper layer. This method is characterized in that the sixth step of forming the film is performed sequentially.

After forming the active part of the field effect transistor on the etching stop layer, the semiconductor substrate is selectively etched away, so the thickness of the semiconductor part of the field effect transistor, which determines the thermal resistance, is uniformly thinned. I can do it.

[Example] The manufacturing process of a field effect transistor which is an example of the present invention will be described below with reference to FIGS. 1(a) to 1(f).

A1°,
ms Ga,, v+ An etching stop layer 2 (thickness = 1 μm) made of an As semiconductor layer, a buffer layer 3 (thickness: 10 μm) made of a high resistance GaAs semiconductor, and a GaAs semiconductor containing silicon with N-type impurities. An active layer 3'' (thickness: 20.15 μm) is sequentially grown epitaxially using an MBE apparatus (Fig. 1(a)).
)AI,...,Ga. , , As the etching prevention layer 2 made of the As semiconductor layer has a composition that can be lattice matched with the GaAs semiconductor.

If necessary, a high resistance and/or low resistance GaAs semiconductor layer is simultaneously grown on the active layer 3'.

An electrode 4 constituting a field effect transistor on the active layer 3'
form. This electrode 4 is composed of a source electrode and a drain electrode that are in ohmic contact with the active layer 3', and a gate electrode that forms a Schottky junction. usually,
Electrodes 4 constituting tens to thousands of field effect transistors are formed on the same substrate 1.

The surface side of the substrate 1 (above the active layer 3' and the electrodes 4) is fixed to a flat support 6 having sufficient rigidity using a wax 5 which serves both as an element protection and adhesive.

Here, as the support 6, a glass plate whose surface is polished flat and wider than the main surface of the substrate 1 is used.

(FIG. 1(b)) Using abrasive grains with a grain size of 20 μm, the back surface of the substrate 1 is mechanically polished so that the thickness of the substrate 1 is 60 μm. Next, board 1
Chemically polish the back side of the plate to a thickness of 30 μm. As the polishing agent (etching liquid), H, SO4
:H,O, :H,0=lO:1:'1 mixture is used. As a result, the unevenness on the back surface of the substrate 1 is within 20 μm.

In the next step, selective etching is performed under the condition that only the substrate 1 made of GaAs is etched and the etching stop layer 2 made of A1°ss Gaa, v+ AS is not etched. This selective etching is SF,: 5i
Reactive ion etching is performed using a mixed gas of C1,=1:50, reaction pressure: 50 mTorr, RF power: 100 W, substrate temperature: 40° C. for 300 minutes. Since the selectivity (etching rate ratio of GaAs/AlGaAs) is about 100, when the substrate 1 is completely removed and the etching prevention layer 2 is exposed, the unevenness on the back surface of the substrate 1 caused by the previous process is etched. On the surface of the blocking layer 2, the unevenness is reduced to within 0.2 μm and becomes sufficiently smooth.

Etching stop layer 2: KI: I: H, 0=1
It is removed using an etching solution of 13:65:100. This etching solution selectively removes AlGaAs and
The buffer layer 3 made of aAs is not etched. (
(FIG. 1(C)) A resist pattern 7 is formed on the exposed buffer layer 3 by photolithography.

This resist pattern 7 is provided corresponding to a region separating a plurality of field effect transistors formed on the substrate 1. Thereafter, a metal layer (Ti/Au) 8 is formed over the entire surface by vapor deposition. (FIG. 1(d)) By removing the resist pattern 7 using a lift-off method, unnecessary portions of the metal layer (Ti/Au) 8 are removed.

Using a solution of NH4OH:H,O,:H, 02:1:100, the buffer layer 3 and active layer 3' are etched for 15 minutes using the metal layer (Ti/Au) 8 as a mask. Thereby, a plurality of field effect transistors formed on the same substrate 1 can be separated.

(FIG. 1(e)) The field effect transistor 9 is peeled off from the support 6. (FIG. 1(f)) The thickness of the field effect transistor created by the above steps (the thickness of the buffer layer 3 and the active layer 3') is lO,8
~11.0 μm, and the thickness variation is 0.2 μm
The following is true. The thickness, which determines the thermal resistance, can be arbitrarily determined by setting the thicknesses of the buffer layer 3 and the active layer 3' during epitaxial growth. Therefore, thermal resistance can be easily reduced. Furthermore, the unevenness of the surface is reduced in the selective etching process, and the uniformity of the back polishing process is improved, so that the uniformity of thermal resistance can be improved.

In the above embodiments, AlGaA is used as the etching prevention layer.
In the present invention, GaAs/AlGaAs is used.

It is possible to adapt to combinations of structures and compositions that allow growth of the active layer, such as AlAs, Ge%Zn5e, etc.

[Effects of the Invention] As explained above, the method for manufacturing a field effect transistor according to the present invention includes the first step of forming an etching stopper layer on one main surface of a semiconductor substrate; a second step of forming a gate electrode, a source electrode, and a drain electrode on the semiconductor layer; a third step of forming a gate electrode, a source electrode, and a drain electrode on the semiconductor layer;
a fourth step of physically and/or chemically etching the other main surface of the semiconductor substrate; etching the semiconductor substrate with an etching means that can obtain a sufficient selectivity between the semiconductor substrate and the etching stopper layer; A fifth step of exposing the etching stopper layer; and a sixth step of forming at least one metal film on the exposed etching stopper layer are sequentially performed.

Therefore, the thermal resistance can be reduced through a simple process, and the uniformity of the thermal resistance can be improved.

[Brief explanation of the drawing]

1(a) to (f) are cross-sectional views for explaining one embodiment of the present invention. In the figures, 1...Substrate, 3...Buffer layer, 4...Electrode, 6. ...Support 8...Metal layer 2...Etching prevention layer, 3'...Active layer, 5...Wax, 7...Resist pattern,

Claims (1)

[Claims] (1) A first step of forming an etching stopper layer on one main surface of the semiconductor substrate; A second step of forming a semiconductor layer on the etching stopper layer; A gate electrode, a source electrode and A third step of forming a drain electrode; A fourth step of physically and/or chemically etching the other main surface of the semiconductor substrate; Etching that provides a sufficient selectivity between the semiconductor substrate and the etching stopper layer. a fifth step of etching the semiconductor substrate by means to expose the etching stopper layer;
and a sixth step of forming at least one metal film on the exposed etching stop layer.