JPS583250A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of a semiconductor device by covering a semiconductor and a metal in a hole formed at an insulating film on a semiconductor substrate and forming both compounds, thereby preventing the disconnection of a wiring layer or an overhang. CONSTITUTION:An electrode windows 12a is opened at an insulating film 12 on a semiconductor substrate made of silicon or the like, a diffused layer 14 is formed, and a polycrystalline silicon film 15 is then coated. Then, the entire surface is anisotropically etched such as by dry etching or the like, thereby allowing a polycrystalline silicon film 15 to remain only in an electrode window, and a metallic film 16 made of platinum or the like is coated thereon. Then, a heat treatment is performed to form a compound 17 of platinum silicide or the like, the unreacted platinum film except the window is removed with aqua regia, and a wire 18 such as aluminum is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming wiring of a semiconductor device without causing disconnection or overhang.

Conventionally, when forming aluminum as a wiring material on a semiconductor/body substrate, the process is as follows.
-), an element is formed on a silicon substrate l, an insulating film 2 such as a silicon oxide film is formed on the entire surface, and then KF! Form a resist f-turn 3 in the desired shape. Next, using a dry etching technique using CF4 gas as the main component of the etchant, the insulating film 2 is selectively etched using the resist pattern 3 as a mask, as shown in FIG. 2(b)K. Thereafter, the resist pattern 3 is removed, and an aluminum film 4 is deposited on the upper surface of the insulating film 2 and silicon substrate 1.

However, the jinno-tane method had the following problems. That is, the etched cross section of the insulating film 2 becomes steep as shown in FIG. 1(b). When an aluminum minilum film 4 is deposited on a surface having such a steep difference, an aluminum film 4 as shown in FIG. 1(C) is formed.
Parts where the film thickness becomes thin tend to occur, and in severe cases, an over-hung structure may be formed as shown in FIG. 3(d). For this reason, there is a problem in that the aluminum wiring layer is likely to be disconnected.

On the other hand, as semiconductor devices become more highly integrated, their element structures are changing from conventional one-dimensional arrays to three-dimensionally laminated structures, such as forming an insulating film between the eyebrows on aluminum wiring. There is a need for a multilayer wiring technology that forms through holes and forms fs second layer aluminum wiring thereon. When forming such a three-dimensional structure, if there is a thin portion of the aluminum wiring or an open structure, the wiring is likely to be disconnected, and voids and cracks in the glabella insulating film are likely to occur. Further, there were problems such as deterioration of pattern forming characteristics near the step difference, deterioration of device processing accuracy such as dry etching, etching during etching, and etching residues, which lowered the reliability of the device.

The present invention has been made in consideration of the above circumstances, and its purpose is to prevent disconnection and overhang of the aluminum wiring layer, and to improve the reliability of the semiconductor device. The purpose is to provide a manufacturing method.

First, the present invention will be explained in detail. In the present invention, after forming a desired opening in an insulating film on a semiconductor substrate, a semiconductor film is selectively formed so as to cover the side surface of the insulating film around the opening, and then a metal is coated on the entire surface of the opening. In this method, the metal is deposited and the semiconductor film is reacted with the semiconductor film to form a compound thereof in the opening, and then the metal on the insulating film is removed. Therefore, the inside of the opening can be filled with a compound of metal and semiconductor film, and the level difference on the surface of the substrate before the wiring process can be significantly reduced. Therefore, it is possible to prevent the occurrence of disconnections and overhangs in the metal wiring, thereby contributing to improving the reliability of the device.

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 2(a) to 2(f) are cross-sectional views showing an aluminum wiring forming process according to an embodiment of the present invention.

First, as shown in FIG. 2(,), a P-type silicon substrate 11 (
1. A silicon oxide film 12 (insulating film) is formed on a semiconductor substrate).
A resist pattern IJ for forming an opening is formed on this silicon oxide film I2. Next, the silicon oxide film 12 is etched using a selective etching technique using the resist holes and turns 13 as a mask to form openings 12-. Then, the above resist pattern 1
After removing the silicon oxide film 12, impurities are introduced into the silicon substrate 11 through the opening 12a using the silicon oxide film 12 as a mask to form a diffusion layer 14 as shown in FIG. 2(b). Here, for example, to introduce phosphorus (P), it is preferable to use a diffusion method using pocls, an ion implantation method, or the like.

Next, as shown in FIG. 2(c), polycrystalline silicon 15 (semiconductor film) is deposited on the upper surfaces of the insulating film 12 and the diffusion layer 14 by about 1 [μmJ] using a vapor phase growth method. And CCl
By etching the entire surface of the substrate using an anisotropic etching technique using 4 gas as the main component of the etchant, polycrystalline silicon 15 is formed only on the side and bottom surfaces of the opening 12m, as shown in FIG. 2(d). The remaining. Next, the deposit layer on the substrate surface generated by the above dry etching was removed using 02
After removal by surface treatment using Glazma, HF aqueous solution, etc., gold 876 (gold Fi) t is deposited on the upper surface of silicon oxide film 12 and polycrystalline silicon 15, as shown in FIG. 2 (-).
1000 [X) 8j HP [do. Next, 550 [℃
] is performed for 15 minutes to react the platinum film 16 and the polycrystalline silicon 15 to form an alloy layer 17 (compound) thereof.

Thereafter, by immersing the silicon substrate 11 in heated aqua regia, the unreacted platinum film 1 on the silicon oxide film 12 is removed.
6 was dissolved, and only the alloy layer 17 remained in the opening 12a as shown in FIG. 2(f). In this way, the level difference due to the opening 121 was reduced and flattened. By depositing the aluminum film 18 as a wiring layer in this state, the second
As shown in Figure (g), the thickness of the aluminum film 18 is approximately uniform.
It will be formed into b.

As described above, according to the method of this embodiment, the alloy layer 17 of polycrystalline silicon 15 and platinum 16 is embedded in the opening 12m formed in the insulation film 12 on the silicon substrate 11. It is possible to reduce the level difference caused by the opening 12S, and thereby the opening 1211 of the sia aluminum film 18 can be reduced.
It is possible to prevent wire breakage and hang-up in advance. Therefore, it is possible to improve manufacturing yield and reliability, and it is extremely effective for multilayer wiring structures. Also,
There is no need for a special mask alignment process when filling the opening 12- with the alloy layer 17, and the process is easy.

Note that the present invention is not limited to the embodiments described above. For example, as shown in FIG. 2(d), the opening 12
Instead of leaving the polycrystalline silicon I6 inside the opening 12m, the polycrystalline silicon 1t may be left only on the side surface of the opening 12m, as shown in FIG. 3(-). Furthermore, it is deposited on the entire surface of the substrate.

When etching the polycrystalline silicon 15 remaining in the opening 12a, the CCl4 gas is used instead of an anisotropic dry etching process in which the main component of the polycrystalline silicon 15 is etched.
Glazma etching using 4 gas glazma and CF4 Q
The multilayer 1A silicon 15 may be left as shown in FIG. 3(b) by using an isotropic dry etching technique such as chemical dry etching mainly containing silicon. Furthermore, when the size of the opening 12a is extremely small (2 μm or less), the polycrystalline silicon 15 deposited inside the opening 12- is smaller than the polycrystalline silicon 15 deposited on the silicon oxide film 12. By taking advantage of the increased film thickness, it is also possible to simplify the process of leaving polycrystalline silicon 15 only within the opening 12m. This is because the polycrystalline silicon 15 on the silicon oxide film 12 is removed in a shorter time than that in the opening 12a. Further, a film 19 having an etch rate approximately equal to that of the polycrystalline silicon I5 is formed by spin coating on the polycrystalline silicon 15 as shown in FIG. 4(-), and then the entire surface is etched by anisotropic dry etching. However, it is also possible to leave some polycrystalline silicon 1 in the opening 12- as shown in FIG. 4(b).

Further, although heat treatment is used to alloy the semiconductor and platinum, it is also possible to use irradiation with a Lede beam, an electron beam, or an ion beam. Furthermore, instead of platinum, KFi, molybdenum, thallium, radium, and various other metals can be used. Furthermore, it goes without saying that the present invention can be applied not only to the process of forming aluminum wiring, but also to the manufacturing process of various semiconductor devices. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of drawings]

1(a) to (d) are cross-sectional views for explaining the conventional method, FIGS. 2(a) to (g) are cross-sectional views showing the wiring forming process according to an embodiment of the present invention, and FIG. Figures (a), (b)
and FIGS. 4A and 4B are cross-sectional views for explaining modified examples. 11... Silicon substrate (semiconductor substrate), 12... Silicon oxide film (insulating film), Jjm... Opening part, 15.
... Polycrystalline silicon (semiconductor film), 16... Platinum film (metal), 17... Alloy film (compound), 18... Aluminum film.

Claims (1)

[Claims] (Li) A step of forming a desired opening in an insulating film formed on a semiconductor substrate, and selectively forming a semiconductor film to cover the side surface of the insulating film around the opening. a step of vapor depositing a metal on the entire surface thereof; a step of reacting the metal with a semiconductor film to form a compound thereof in the opening; and then removing the metal on the insulating film. (2) A process line for selectively forming the semiconductor film, the semiconductor substrate, and the insulating film. A method for manufacturing a semiconductor device according to claim 1, characterized in that a semiconductor film is formed on the entire surface of the substrate, and then the entire surface is subjected to dry etching and etching. (3) The semiconductor substrate and the semiconductor film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein silicon is used as the metal and gratina is used as the metal.