JPS61105793A - Memory device - Google Patents

Abstract

PURPOSE:To initialize the memory cells easily and in a short time regardless of the memory capacity by selecting all the addresses of the memory cells of an RAM simultaneously and initialize by writing the same value. CONSTITUTION:When the control signal S is made H, the outputs A1-An of the OR-gate 4 of the row address control circuit become H regardless of the address decode signal a1-an. The outputs of the OR-gate 5 of the column address control circuit also become H. The outputs of the NOR-gate 6 of the write control circuit become L regardless of write data DA. When the write enable signal WE becomes H, L is written in all the memory cells of the RAM, and initialize them in cleared status. The initialization of the RAM in H-level is performed likewise, and eliminates a complicated reset circuit and the likes. Thus the memory cells of the RAM built in the memory device of IC are easily and briefly initialized regardless of the memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated circuit having a built-in RAM, such as a microcomputer integrated on one chip, in which all memory cells of the built-in RAM are simultaneously set to the same value. Regarding an integrated circuit that has the function of setting the initial state of all memory cells by writing The initial state is undefined. Therefore, it is necessary to set the initial state of each memory cell as necessary. Generally, a low level is often written to all memory cells as an initial state setting (hereinafter referred to as clear).
.

In the case of a microcomputer integrated on one chip, in order to clear all memory cells, use the instructions of the microcomputer to clear one basic word length (1 basic word length if the basic word length is 8 bits) using software. I have to clear it one by one.

Therefore, if the memory capacity is large, it takes a long time.

In order to compensate for the above-mentioned drawbacks, memory cells having a reset function have conventionally existed. FIG. 1 shows an example of a conventional memory cell having a reset function. Still, FIG. 2 shows an example of a memory cell without a reset function. Originally,
The memory cell can be configured with two inverter gates 1 and two transfer gates 3 as shown in FIG. , one NOR gate 2 is required instead of one inverter gate. This d:, when converted to the number of transistors, it is 1 in the case of Nch MOS, and 1 in the case of C-MO
In the case of S, the number increases by two. An extra reset signal line is still required.

As described above, the conventional memory cell with the glue set function has a large amount of circuitry, which increases the area occupied on the chip.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide an integrated circuit having a function of easily setting the initial states of all memory cells.

Structure of the Invention The present invention includes means for simultaneously selecting the addresses of all memory cells, regardless of the address signal input to the RAM, and by writing the same value to all memory cells at the same time, the entire memory This allows the initial state of the cell to be set.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a block diagram of the present invention. Address signal AD
is input to the row address decoder (■) and column address decoder (■). In normal use, both the gender and column address decoders provide the row address decode signal a1.
~al and column address decode signals α1 to αm are decoded to select one of the memory cells. In this case, the row address control circuit (1) transmits the address decode signals a1-al as they are to the memory cell array (2) as signals 1-An. One set of column address control circuits (2) is still selected, and the write control circuit (2) transmits the fill-in data DA as is. When clearing a memory cell, a control signal S is input. In this case, row address control circuit (2) selects all signals A1-An regardless of row address decode signals a1-an. In addition, the column address control circuit V controls the data signal line pair (Dl, D
All pairs of l) to (De, De) are selected. In the write control circuit (2), a low level is transmitted regardless of the write data DA. By the above-described operation, a low level can be simultaneously written to all memory cells in the memory array (1). FIG. 4 shows a circuit diagram of an embodiment of the present invention.

In this figure, 4 is an OR gate that constitutes a row address control circuit, 5 is an OR gate that is a column address control circuit, and 6 is an OR gate that constitutes a column address control circuit.
O8 is a NOR gate that constitutes a write control circuit.
is a control signal for clearing the memory cell. In normal use, the control signal S is kept at a low level.

In this case, one of the row address decode lines a1 to al becomes high level by the row address decoder, and the OR gate 4 in the row address control circuit
tA+ to An. The column address decode lines α1 to α are still output by the column address decoder. One of the signals becomes a high level, and the OR gate 5 in the column address control circuit v goes to α1 to α. are directly transmitted to the same column address control circuit v as selection signals β1 to βm. On the other hand, in the write control circuit, the write data DA is passed through the NOR gate 6. , 6 and 7 are transmitted. Therefore, when the write enable signal WE becomes high level, the write data DA is written into the memory cell designated by the row address and column address.

Next, when clearing the memory cell, the control signal S is set to high level. In this case, O in the row address control circuit ■
In the R gate 4, all of A1 to An are set to high level regardless of address decode signals a1 to an. Similarly, in the OR gate 5 in the column address control circuit v, β1 to
Set all of βm to high level. On the other hand, the NOR gate 6 of the write control circuit (2) transmits a low level regardless of the write data DA. Therefore, when the write enable signal WE goes high, a low level is written to all memory cells.

The above explanation deals with clearing a memory cell, but when setting a memory cell (writing a high level), the write control circuit must transmit a high level regardless of the write data when setting. Bye.

As an embodiment of the present invention, FIG. 4 shows the case of Nch-MOS, but the same applies to C-MOS.

Effects of the Invention According to the present invention, by simply adding a simple control circuit, the initial states of all memory cells can be set in a short time regardless of the capacity of the memory.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional memory cell with seven functions.
FIG. 2 is a circuit diagram of a general memory cell having a beam setting function, FIG. 3 is a block diagram of a device according to an embodiment of the present invention, and FIG. 4 is a circuit diagram showing an embodiment of the present invention. 1...inverter game), 2.6...NO
R game-l-, 3...transfer game), 4.
ts...OR gate, ■...Row address decoder, ■...Row address control circuit, ■...
Memory cell array, ■・・・Column address decoder,
■・・・Column address control circuit, ■・・・Write control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] A memory device incorporating a RAM is provided with means for simultaneously selecting the addresses of all memory cells, regardless of the address signal input to the RAM, and by writing the same value to all the memory cells at the same time. A memory device characterized by having a function of setting an initial state of a memory cell.