JPS61105171A - Picture compressing device - Google Patents

Abstract

PURPOSE:To effectively utilize the compression code output area by immediately holding the state and stopping the operation when the code output area is overflowed during compression operation and restarting the picture compressing operation after transferring the compression codes to a recording medium such as optical disk. CONSTITUTION:When a direct memory access controller DMAC2 receives starting signal from a host unit, it fetches compression modes MH, MR, picture information top address, number of picture information data, code output area top address, and number of code output area spaces, calculates and output a shift control parameter 8 to shift the picture data, and outputs a operation mode 9 to a picture compressing part 3. Then, after giving the processing starting action 7 to the image compressing part 3, it waits for READ/WRITE request signal 6, and when it receives the READ/WRITE request signal 6 from a picture compressing part 3, it conducts READ/WRITE access control of the picture data and compression codes in the picture information storing memory 1.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to an image compression device.

[Background of the invention]

When compressing an image, it is difficult to predict the number of compression codes because the compression code varies depending on the number of pixel color changes in the image. Conventionally, the code output area for transmission to a recording medium such as an optical disk was set to a sufficiently large space equivalent to a page or several lines of one image. Due to the increased capacity of the code output area, there was no consideration given to wasted space in the code output area. A related device of this type is JP-A No. 58-5472.

[Purpose of the invention]

An object of the present invention is to provide a means for effectively utilizing a compressed code amount canilia for transferring an image compression code to a recording medium such as an optical disk.

[Summary of the invention]

In order to achieve the above object, the image compression device of the present invention includes a memory for storing image information and compression codes, and controls information read/write control, memory address management, and image compression operation for the memory. As soon as it reaches the final address of the code pressure caniglia, it stops the compression operation while retaining that state, and restarts it later, and it actually executes the image compression and retains its internal state as soon as it receives a stop command. By providing a means to continue compression operation upon receiving a restart command, the compression code ratio can be effectively utilized.

Implementation sequence of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an image compression device showing an embodiment of the present invention. In FIG. 1, 1 is an image information storage memory that stores images, compression codes, etc., 2 is a DMAC, and 3 is a
4 is a 24-bit address bus. 5 is a 16-bit data bus. 6 is R, EAD-WR, IT.
E request signal, 7 is processing start activation, 8 is shift control parameter, and 9 is operation mode information.

When the DMAC 2 receives the activation signal from the host device, the DMAC 2 reads the compression mode (MH, MR), image information start address, image information data number, and code pressure canilia start address from the image information storage memory.

calculation and output of a shift control parameter 8 for taking in the sign ratio Canilia space number and shifting the image data;
and operation mode 9 are output to the image compression section 3. Next, after processing the image compression unit 3 and applying the processing start operation 7, READ-
Waiting for the WRITB request signal 6, and upon receiving the READ-WRITE request signal 6 from the 1-image compression unit 3, performs R, EAD-WRITE access processing with the 1-image information storage memory 1, 1 image data and compression code image information storage memory 1. Manage addresses within.

Also, at that time, the address in the image information storage memory 1 where the compression code should be output is ticked, and if it is the last of the specified output space, the information in the register in itself (2, DMAC) is immediately stored in the image information storage memory. It is saved in the work area of the memory 1 and sends an operation stop command (included in the operation mode information 9) to the image compression section 3.

The image compression section 3 receives the processing start signal 7 from the DMAC 2, and performs an image compression operation using the configuration shown in FIG.

In FIG. 2, image data is stored in image information storage memory 1.
After being set in the read data buffer 10 via the data bus 5, the fi column (P) is converted into serial (8),
The MH compression unit 12. M.R.
The data is input to the compression unit 13.

The MH compression section 12, the MR compression section 130, and the compression section 130 are controlled by the clock control il1 section 17, and convert the image data into MH and M
R, code and sends code information to 14 selectors.

The code information selected by the 1B operation mode register is converted from 15 serial (S) to parallel (P) and set to 16 write data.

The 17-speed control unit first receives the 8 shift control parameters from the 2DMAC, sets the initial state for performing all shift control of the image compression unit, and then receives the 8th shift control parameter from the 2nd DMAC.
Processing in step 7 from MAC □Receives the start activation signal, starts each unit operation for image compression, controls the shift clock of each unit, and sends 23 RFiAD-WRIITB requests to 19 R, BAD-WRITE request control circuits. 19 READ-WR, IT' that sends sector signals
The D request control circuit receives 23 R, BAD/WRITE request set signals from 17 clock control and 20 compression operation permission signals from 18 operation mode registers, and receives 6 READ signals for 2 DMACs. -WR, I'l'E
25 if the request signal is sent and the compression operation permission signal of 20 is not received.
The WRITFf request sector signal of 2 is accepted.
The WRIT request signal of 6 cannot be sent to the DMAC of 17.
Immediately stop the 22 basic diad clocks that are output to both clock control sections.

18 operation mode registers receive 9 operation mode information (MH mode, MR mode, etc.) from 2 DMACs, and 1
Send to selector 4. Further, when an operation stop command (included in the operation mode information 9) is received from the DMAC 2, the compression operation permission signal 20 outputted to the READ/WRITE request control circuit 19 is immediately reset.

FIG. 5 shows the main circuits in the 19 READ-WR, ITE request control circuits, and FIG. 4 shows their time charts, which are the characteristics of the present invention. The specific operations of interruption and continuation of the compression operation will be explained.

In FIG. 3, 27 basic clocks are received from 17 clock controls, 28 read backs 7 assets and 29 write buffers 1 set are received from 2 DMACs.

In FIGS. 3 and 4, first, by resetting 26, 24 R, EADREQF, F, and 25 WRITE are reset.
R, EQF, and F are reset and a 220 basic shift clock is output.

Next, the 230RE A D request sector signal becomes 11', and 24 R, BADREQF, F are set and 20
The AND condition with the compression operation permission signal results in 6 READ request signals 1'.

At the same time, the 22 basic shift clocks are stopped.

Next, at the same time as the memory read access of DMAC 2 ends, the 71st sector of the 28th band becomes 11', and with the AND condition with the compression operation permission signal of 20, the R, BADR of 24
EQF and F are reset, the READ request signal of 6 becomes 10', and the 220 basic shift clock starts operating.

Regarding the 6 WR and ITE request signals, 23 BEAD
The request sector signal is set to 23's WR, ITE request sector signal, and the 2nd day's read back 71 set is set to 29's write band 71.
Replace it with set and perform the same operation.

Next, the 6th WR, ITE request signal is output to the 2nd DMAC, and when the end of the code output area is detected by the 2nd DMAC, the 20th compression operation permission signal becomes 01, and the 25th DMAC becomes 01. WR, ITERBQF, F.

remains set as 6 WR, ITE request signal as 10'
The basic shift clock 22 also remains stopped.

Next, when the compression operation permission signal of 20 becomes 11', the W of 6
At the same time that the RITE request signal becomes 11' and the memory write access ends, the write back 7 assets of 29 become 11'.
25 WRITE REQF, F.

is reset and the 22 basic shift clocks start operating again.

[Effects of the Invention] As explained above, according to the present invention, it is possible to interrupt and continue the image compression operation. Since the compression operation is immediately interrupted and restarted by the DflilAC activation command, the final data in the code output area does not need to be the line end code of the image data, and may be in the middle of the code.

Therefore, the code output area can be used more effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image compression device according to an embodiment of the present invention, FIG. 2 is an internal configuration diagram of an image compression unit, and FIG. ,EAD-W
R, ITE request system circuit diagram, Figure 4 is its time chart. 1... Image information storage memory, 3... Image compression section, 4
...address bus, g...data bus, ?
...Processing start signal. 8... Schiff) 1ri! Ii [parameter, 9...operation mode, 12...MH pressure section 13...M
FL compression section, 14... Selector, 17... Clock control section, 21... Compression operation mode, 22...
Basic shift, 26... Reset signal, 27.
...Basic clock, 29...Write buffer set signal.

Claims (1)

[Claims] 1. In a device that compresses image data using the MH/MR method, a memory that stores image information and compression codes;
DMAC (Direct Memory Acc
essController) and an image compression unit that receives a start signal from the DMAC and actually executes image compression.In order to effectively utilize the area for outputting image compression codes, the code output area overflows during compression operation. An image compression device characterized in that, when a compression code is detected, the image compression device immediately maintains the state, stops the operation, transfers the compression code to a recording medium such as an optical disk, and then resumes the image compression operation.