JPS6110338Y2 - - Google Patents

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Publication number
JPS6110338Y2
JPS6110338Y2 JP1546879U JP1546879U JPS6110338Y2 JP S6110338 Y2 JPS6110338 Y2 JP S6110338Y2 JP 1546879 U JP1546879 U JP 1546879U JP 1546879 U JP1546879 U JP 1546879U JP S6110338 Y2 JPS6110338 Y2 JP S6110338Y2
Authority
JP
Japan
Prior art keywords
input
hybrid circuit
output
circuit
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1546879U
Other languages
Japanese (ja)
Other versions
JPS55115112U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1546879U priority Critical patent/JPS6110338Y2/ja
Publication of JPS55115112U publication Critical patent/JPS55115112U/ja
Application granted granted Critical
Publication of JPS6110338Y2 publication Critical patent/JPS6110338Y2/ja
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は入力用ハイブリツド回路の2つの出力
端子に単位増幅器と受動回路網を接続することに
より整合を行なつた小形で特性の優れたマイクロ
波増幅装置に関するものである。
[Detailed description of the invention] The present invention relates to a small microwave amplification device with excellent characteristics, which performs matching by connecting a unit amplifier and a passive circuit network to two output terminals of an input hybrid circuit. .

従来、電界効果トランジスタ(FET)等を用
いたマイクロ波増幅器は、たとえば第1図に示す
ように、FET3のゲート入力側は直列インダク
タンスと並列容量より成る入力整合回路2を介し
て入力端子1に接続され、FET3のドレイン出
力側は2と同様の出力整合回路4を介して出力端
子5に接続される。この場合、FETの特性とし
て出力側インピーダンスは比較的高く整合がとり
易いのに対し、入力側インピーダンスは低く必要
な周波数帯域で整合をとることが非常に難しい。
この傾向はとくに高出力になるほど著しい。
Conventionally, in a microwave amplifier using a field effect transistor (FET) or the like, as shown in FIG. The drain output side of FET 3 is connected to output terminal 5 via output matching circuit 4 similar to 2. In this case, as a characteristic of the FET, the output side impedance is relatively high and it is easy to match, whereas the input side impedance is low and it is very difficult to match in the necessary frequency band.
This tendency is particularly noticeable as the output increases.

そこで従来は第2図に示すように、2個のハイ
ブリツド回路11,12の各1対の入出力端子間
に1対の単位増幅器13,14を接続し、ハイブ
リツド回路11の入力側に入力端10と無反射終
端15を、ハイブリツド回路12の出力側に出力
端20と無反射終端16を設けていた。この場合
両増幅器13,14の合成出力が取り出され、そ
の入出力における反射波は各ハイブリツド回路1
1,12の無反射終端15,16で吸収されるか
ら実効的に入出力のインピーダンス改善が行なわ
れ、良好な特性のマイクロ波増幅装置が得られ
る。
Therefore, conventionally, as shown in FIG. 2, a pair of unit amplifiers 13 and 14 are connected between each pair of input and output terminals of two hybrid circuits 11 and 12, and an input terminal is connected to the input side of hybrid circuit 11. 10 and a non-reflection termination 15, and an output end 20 and a non-reflection termination 16 were provided on the output side of the hybrid circuit 12. In this case, the combined output of both amplifiers 13 and 14 is taken out, and the reflected waves at the input and output of each hybrid circuit 1
Since it is absorbed by the non-reflection terminations 15 and 16 of No. 1 and No. 12, the impedance of input and output is effectively improved, and a microwave amplification device with good characteristics can be obtained.

しかしながら、この方式は、同一利得を得るの
に2個の単位増幅器を必要とし、消費電力の増
加、形状の大形化、高価格化等の不都合を伴な
い、とくに多段使用の場合には問題となる。
However, this method requires two unit amplifiers to obtain the same gain, and has disadvantages such as increased power consumption, larger size, and higher price, which is a problem especially when used in multiple stages. becomes.

本考案の目的は1個の単位増幅器を用いて十分
安定な整合を行ない小形で特性の優れたマイクロ
波増幅装置を提供することである。
An object of the present invention is to provide a small-sized microwave amplification device with excellent characteristics, which performs sufficiently stable matching using one unit amplifier.

前記目的を達成するため、本考案のマイクロ波
増幅装置は方向性結合器によりハイブリツド回路
の入力側の一端を信号の入力端子とし、該ハイブ
リツド回路入力側の他の端子に無反射終端を接続
し、該ハイブリツド回路の出力側の一端にマイク
ロ波増幅器を接続し、該ハイブリツド回路の出力
側の他の一端に該マイクロ波増幅器の入力インピ
ーダンスと等しい入力インピーダンスを持ち整合
回路と無反射終端からなる受動回路網を設けたこ
とを特徴とするものである。
In order to achieve the above object, the microwave amplifier of the present invention uses a directional coupler to make one end of the input side of a hybrid circuit a signal input terminal, and connects a non-reflection termination to the other terminal of the input side of the hybrid circuit. A microwave amplifier is connected to one end of the output side of the hybrid circuit, and a passive circuit consisting of a matching circuit and a non-reflection termination having an input impedance equal to the input impedance of the microwave amplifier is connected to the other end of the output side of the hybrid circuit. The feature is that a circuit network is provided.

以下本考案を実施例につき詳述する。 The present invention will be described in detail below with reference to examples.

本考案は第1図に示したようなマイクロ波増幅
器に用いられるFETやバイポーラトランジスタ
等の能動3端子素子が通常入力インピーダンスは
低いが、出力インピーダンスは比較的高く出力側
の整合回路の実現にとくに問題がなく、第2図に
示したような出力側のハイブリツド回路12を省
き受動回路網としても十分満足すべき整合が得ら
れることに基づくものであり、これに関連して単
位増幅器を1個のみとすることができるものであ
る。
The present invention is particularly useful for realizing matching circuits on the output side, where active three-terminal elements such as FETs and bipolar transistors used in microwave amplifiers as shown in Figure 1 normally have low input impedance, but relatively high output impedance. This is based on the fact that there is no problem and that a sufficiently satisfactory matching can be obtained even as a passive network by omitting the hybrid circuit 12 on the output side as shown in Fig. 2.In connection with this, one unit amplifier can be used. It is only possible to do so.

第3図は上述の原理に従う本考案の実施例の構
成を示す説明図である。
FIG. 3 is an explanatory diagram showing the structure of an embodiment of the present invention according to the above-mentioned principle.

同図において、第2図と同様のハイブリツド回
路11の2つの入力端子の一方11−1に入力端
10を、他方11−2に無反射終端25を接続
し、2つの出力端子のうち一方の11−4を単位
増幅器21に接続して出力端20より出力を取出
すとともに、他方の11−3を整合回路23と無
反射終端24より成る受動回路網22に接続す
る。この受動回路網22の構成は単位増幅器21
の入力側すなわちハイブリツド回路11の一方の
出力端子11−4での反射係数と、ハイブリツド
回路11の他方の出力端子11−3での反射係数
とが等振幅、同位相となるように設定され、その
結果ハイブリツド回路11の入力端子11−1に
おいては等振幅、逆位相となり増幅装置としての
入力インピーダンスを改善することになる。
In the figure, the input terminal 10 is connected to one of the two input terminals 11-1 of a hybrid circuit 11 similar to that in FIG. 11-4 is connected to a unit amplifier 21 to take out an output from an output terminal 20, and the other 11-3 is connected to a passive network 22 consisting of a matching circuit 23 and a non-reflection termination 24. The configuration of this passive circuit network 22 is that the unit amplifier 21
The reflection coefficient at the input side of the hybrid circuit 11, that is, one output terminal 11-4 of the hybrid circuit 11, and the reflection coefficient at the other output terminal 11-3 of the hybrid circuit 11 are set to have the same amplitude and the same phase, As a result, the input terminal 11-1 of the hybrid circuit 11 has equal amplitude and opposite phase, which improves the input impedance of the amplifier.

以下、第1図の単位増幅器を用いて特性改善を
行なつた本考案の特性の検討結果につき説明す
る。
Hereinafter, the results of examining the characteristics of the present invention, which has improved characteristics using the unit amplifier shown in FIG. 1, will be explained.

第4図は第1図の回路による6GHz帯の単位増
幅器の周波数を変化した場合の利得、入力
VSWR、出力VSWRの値を示す。すなわち、周波
数5.7〜6.3GHzで利得13dB±0.2dB、入力VSWR4
以下、出力VSWR1.4以下となる。
Figure 4 shows the gain and input when changing the frequency of the 6GHz band unit amplifier using the circuit in Figure 1.
VSWR, indicates the output VSWR value. i.e. gain 13dB±0.2dB at frequency 5.7~6.3GHz, input VSWR4
Below, the output VSWR will be 1.4 or less.

この単位増幅器を用いて第3図に示した本考案
の構成によつて入力インピーダンスを改善した結
果を第5図、第6図に示す。
FIGS. 5 and 6 show the results of improving the input impedance using this unit amplifier according to the configuration of the present invention shown in FIG. 3.

第5図は3dBハイブリツド回路を用いたもので
ある。この場合は5.7〜6.3GHzで利得10.1±
0.2dB、入力VSWR1.2以下、出力VSWR1.5以下
が得られた。
Figure 5 uses a 3dB hybrid circuit. In this case, the gain is 10.1± from 5.7 to 6.3GHz.
0.2dB, input VSWR of less than 1.2, and output VSWR of less than 1.5 were obtained.

第6図は2dBハイブリツド回路を用いたもので
ある。この場合は5.7〜6.3GHzで利得11dB±
0.2dB、入力VSWR1.4以下、出力VSWR1.7以下
が得られた。利得については、第5図、第6図の
例では単位増幅器の場合に比べてそれぞれ約
3dB,2dBの低下となつている。
Figure 6 uses a 2dB hybrid circuit. In this case, the gain is 11dB± from 5.7 to 6.3GHz.
0.2dB, input VSWR of less than 1.4, and output VSWR of less than 1.7 were obtained. Regarding the gain, in the examples shown in Figures 5 and 6, each is approximately approximately
The decrease is 3dB and 2dB.

しかしながら、単位利得当りの消費電力では従
来例に比べて第5図の場合で65%、第6図の場合
で59%に低減されることになる。この効果はとく
に多段接続された高利得の増幅装置の場合には顕
著となる。
However, the power consumption per unit gain is reduced to 65% in the case of FIG. 5 and 59% in the case of FIG. 6 compared to the conventional example. This effect is particularly noticeable in the case of high-gain amplifiers connected in multiple stages.

たとえば、単位増幅器の消費電力をPuとする
と、従来例では4個のFETを用いて26dBの利
得、4Puの消費電力となるが、3dBハイブリツド
を用いた本考案によると、3個のFETを用いて
30dBの利得、3Puの消費電力となり、2dBハイブ
リツドを用いた場合には3個のFETを用い33dB
の利得、3Puの消費電力となる。
For example, if the power consumption of a unit amplifier is Pu, the conventional example uses 4 FETs and has a gain of 26 dB and the power consumption of 4 Pu, but according to the present invention using 3 dB hybrid, 3 FETs are used and the power consumption is 4 Pu. hand
The gain is 30dB, the power consumption is 3Pu, and when using a 2dB hybrid, it is 33dB using 3 FETs.
The gain is 3Pu, and the power consumption is 3Pu.

なお、実施例ではブランチ形(またはハイブリ
ツドリング形)のハイブリツド回路を用いた例に
ついて示したが、分布結合形の方向性結合器を用
いても全く同様の効果が得られる。
In the embodiment, an example using a branch type (or hybrid ring type) hybrid circuit is shown, but exactly the same effect can be obtained by using a distributed coupling type directional coupler.

以上説明したように、本考案によれば、入力用
ハイブリツド回路の2つの出力端子に単位増幅器
と受動回路網を接続して整合を行ない入力インピ
ーダンスの改善を行なうことにより、特性の改善
とともに単位増幅器数の減少、小形化、消費電力
の低減、低価格化等に資するところが大きい。
As explained above, according to the present invention, by connecting a unit amplifier and a passive network to the two output terminals of an input hybrid circuit and performing matching to improve the input impedance, the unit amplifier This greatly contributes to reduction in number, downsizing, power consumption, and cost reduction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の単位増幅器の構成説明図、第2
図は従来のマイクロ波増幅装置の構成説明図、第
3図は本考案の実施例の構成説明図、第4図は従
来の単位増幅器の特性図、第5図、第6図は本考
案の実施例の特性図を示し、図中、10は入力
端、11はハイブリツド回路、20は出力端、2
1は単位増幅器、22は受動回路網、23は整合
回路、24,25は無反射終端を示す。
Figure 1 is an explanatory diagram of the configuration of a conventional unit amplifier;
The figure is an explanatory diagram of the configuration of a conventional microwave amplification device, Figure 3 is an explanatory diagram of the configuration of an embodiment of the present invention, Figure 4 is a characteristic diagram of a conventional unit amplifier, and Figures 5 and 6 are diagrams of the configuration of an embodiment of the present invention. A characteristic diagram of the embodiment is shown, in which 10 is an input terminal, 11 is a hybrid circuit, 20 is an output terminal, 2
1 is a unit amplifier, 22 is a passive circuit network, 23 is a matching circuit, and 24 and 25 are non-reflection terminations.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 方向性結合器によりハイブリツド回路の入力側
の一端を信号の入力端子とし、該ハイブリツド回
路入力側の他の端子に無反射終端を接続し、該ハ
イブリツド回路の出力側の一端にマイクロ波増幅
器を接続し、該ハイブリツド回路の出力側の他の
一端に該マイクロ波増幅器の入力インピーダンス
と等しい入力インピーダンスを持ち整合回路と無
反射終端からなる受動回路網を設けたことを特徴
とするマイクロ波増幅装置。
Using a directional coupler, one end of the input side of the hybrid circuit is used as a signal input terminal, a non-reflection termination is connected to the other terminal of the input side of the hybrid circuit, and a microwave amplifier is connected to one end of the output side of the hybrid circuit. A microwave amplification device characterized in that a passive circuit network having an input impedance equal to the input impedance of the microwave amplifier and consisting of a matching circuit and a non-reflection termination is provided at the other end of the output side of the hybrid circuit.
JP1546879U 1979-02-09 1979-02-09 Expired JPS6110338Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1546879U JPS6110338Y2 (en) 1979-02-09 1979-02-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1546879U JPS6110338Y2 (en) 1979-02-09 1979-02-09

Publications (2)

Publication Number Publication Date
JPS55115112U JPS55115112U (en) 1980-08-14
JPS6110338Y2 true JPS6110338Y2 (en) 1986-04-03

Family

ID=28837221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1546879U Expired JPS6110338Y2 (en) 1979-02-09 1979-02-09

Country Status (1)

Country Link
JP (1) JPS6110338Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007535828A (en) * 2003-03-28 2007-12-06 アンドリュー・コーポレーション High efficiency amplifier and design method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007535828A (en) * 2003-03-28 2007-12-06 アンドリュー・コーポレーション High efficiency amplifier and design method thereof
JP4870556B2 (en) * 2003-03-28 2012-02-08 アンドリュー・リミテッド ライアビリティ カンパニー High efficiency amplifier and design method thereof

Also Published As

Publication number Publication date
JPS55115112U (en) 1980-08-14

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