JP2994231B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of obtaining highly efficient amplification in the UHF band.

[0002]

2. Description of the Related Art FIG. 3 shows "900 MHz tygallium scale", Kodichiba et al., Embry. 83-24 (900 MHz band GaAs high efficiency power amplifier MW83-24, IEICE Technical Report 1983) It is a circuit diagram of a semiconductor device using the shown conventional field effect transistor (hereinafter abbreviated as FET). The leased-grounded FETs 1 and 2 each have a gate terminal G, a source terminal S, and a drain terminal D. Distributed constant lines 5, 6, 22, 23, interstage matching circuit 2
2. The input matching circuit 23, the distributed constant lines 5 and 6, and the open stubs 8 and 9 form an output matching circuit.

According to this circuit, the characteristic impedance is changed by adjusting the length and width of the distributed constant lines 5, 6, 22, and 23 and the short stubs 8 and 9 with respect to the fundamental frequency f ₀ to be amplified. Matching conditions. Further, in the output matching circuit composed of the distributed constant lines 5 and 6 and the open stubs 8 and 9, the distributed constant line 5 and the open stub 8 provide a frequency 3f which is three times the fundamental wave at the drain end of the FET2.
_{At 0} , a load condition close to infinite impedance is given, and furthermore, a load condition close to a short circuit at a frequency 2f ₀ twice the fundamental wave is given by the distributed constant lines 5, 6 and the open stubs 8, 9. .

For this reason, the frequency components twice and three times the fundamental wave are unnecessary radiation, but they are reflected by the output matching circuit, back injected into the drain terminal D of the FET 2 again, and superimposed on the fundamental wave component. Harmonic processing is realized. Therefore, according to this circuit, a drain efficiency higher by 30% or more is obtained as compared with an amplifier circuit in which the processing of 2f ₀ and 3f ₀ is not performed. In a UHF band power amplifier such as a mobile communication device, which must be reduced in size and weight, high-frequency power is efficiently generated from a limited battery capacity and voltage by using such a technique.

[0005]

In the circuit of the invention Problems to be Solved The conventional semiconductor device, a short circuit only by the output-side matching circuit elements for impedance matching and 2f ₀ for f _0, it is necessary to achieve a condition of opening for 3f _0, It is very difficult to accurately achieve the ideal load condition, and in reality, f
Matching the 2f ₀ of _0, the processing of 3f ₀ operation is forced in an incomplete state. In particular, an FET that generates high-frequency output power of about 1 W, such as a mobile communication device, cannot be ignored because of poor isolation between input and output, so that the output matching condition and the input matching condition cannot be given completely independently. That is, some harmonic processing is indispensable not only for the load condition of the output-side matching circuit but also for the input-side matching circuit to improve the efficiency.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
First and second field effect transistors, and first field effect transistor
Connected between the input terminal of the transistor and the first terminal.
Input matching circuit and output terminal of second field effect transistor
An output matching circuit connected between the first and second terminals;
The output terminal of the field effect transistor and the second field effect transistor
An interstage matching circuit connected between the input terminals of the
The output matching circuit is connected to the output of the second field-effect transistor.
First and second terminals connected in series between the power terminal and the second terminal;
Connection between the distributed constant line and the first and second distributed constant lines
A third distributed constant line having one end connected to the point,
At least twice the frequency of the fundamental wave
The frequency component twice the fundamental wave is reflected by the output matching circuit and
Back-injected into the output terminal of field-effect transistor 2
In a semiconductor device that performs harmonic processing in which components are superimposed,
The step-matching circuit includes at least a first field-effect transistor.
Between the output terminal of the transistor and the input terminal of the second field-effect transistor.
Fourth and fifth distributed constant lines connected in series to
An end is connected to a connection point with the fourth and fifth distributed constant lines.
A sixth distributed constant line, and a second field effect transformer.
Harmonic processing is also performed on the input side of the transistor.
You .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. Reference numerals 1 and 2 denote lease grounded FETs having a gate terminal G, a drain terminal D, and a lease terminal S, respectively. 5, 6, 7, 8, and 9 are distributed constant lines,
10 and 11 are capacitors for short-circuiting 8 and 9 in high frequency. The elements 5, 6, 7, 8, 9, 10, and 11 constitute an output matching circuit, and are connected to the drain terminal of the FET2. 12, 13, 14, 15, and 3 are distributed constant lines, and 3 and 16 are capacitors for short-circuiting 4 and 15, respectively. 3,4,12,13,1
Reference numerals 4 and 15 constitute an interstage matching circuit, that is, an input matching circuit of FET2, and are connected between the drain terminal of FET1 and the gate terminal of FET2. 17, 18, 19
Is a distributed constant line, and 20 is a capacitor for short-circuiting 19. The components 17, 18, 19 and 20 constitute an input matching circuit and are connected to the gate terminal of the FET1. 21
Is a capacitor that blocks direct current between FET1 and FET2.

The high-frequency signal of frequency f ₀ supplied from the input terminal 22 of the semiconductor device is transmitted to the gate terminal G of the FET 1 with a small loss by the input matching circuit, is effectively amplified, and appears at the drain terminal D. Inter-stage matching circuit and an output matching circuit in similarly small loss, or to effectively transmit high-frequency signals to obtain a large output power, f ₀
Aligned against.

Also, distributed constant lines 5 and 6 and capacitor 11
The short stub configured as follows gives a high impedance close to infinity to 3f ₀ to the drain terminal of the FET 2, and the distributed constant line 5 and the capacitor 10 provide an impedance close to a short circuit to 2f ₀ . Further, among the elements constituting the interstage matching circuit, the distributed constant line 4 and the capacitors 3 and 31 give an impedance close to a short circuit at 2 f ₀ to the gate terminal of the FET 2.

As a result, the high-frequency component generated at the output terminal 23 is reflected by the FET 2, achieving more ideal superimposition of higher harmonics and realizing highly efficient amplification. For example, ε = 9.8
In the case where a 900 MHz band semiconductor device is constructed using the alumina ceramic substrate of FIG.
If the capacitor 3 is made of a copper pattern having a length of 1.85 mm and the capacitor 3 is set to 1000 pF and the capacitor 31 is set to 4 pF, even if a 1005 type chip capacitor is used, a high frequency of 1.8 GHz which is twice the fundamental wave 900 MHz can be effectively obtained. Can be processed.

Here, the capacitor 3 achieves a low impedance with respect to the fundamental frequency, but doubles 1.8 GHz.
In the vicinity of z, an effect appears as an inductor component due to the structure of the chip capacitor, so that the capacitor 31 compensates for low impedance at a high frequency.

FIG. 2 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention. In this embodiment, 1 is a source-grounded FET, and 2 is a gate-grounded FET, which constitutes a cascode-type amplifier circuit. The configuration and operation of the input matching circuit and the output matching circuit are the same as those of the embodiment of FIG.
, And 4 functions as an open stub.

In a cascode type amplifier circuit, an interstage matching circuit is generally not provided, and FETs in the preceding and succeeding stages are directly connected in many cases. However, in the matching circuit of this embodiment, a distributed constant line is used for double harmonic processing. . The open stub 4 gives an impedance near 2f ₀ to a short circuit at the lease terminal of the FET 2. Therefore, as in the case of the short stub shown in the embodiment of FIG. 1, more ideal harmonic processing is achieved and high-efficiency amplification is realized.

[0015]

As described above, according to the present invention, since the resonance circuit for short-circuiting even-order harmonics is provided on the transmission line of the input matching circuit of the FET, the fundamental wave f ₀ realized by the output side circuit is provided.
Matching, short circuit 2f _0, in addition to the opening of 3f _0, thereby realizing a short circuit 2f ₀ at the input side. For this reason, it is possible to obtain a higher drain efficiency than the harmonic processing achieved only under the output load condition of the FET.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional semiconductor device.

[Explanation of symbols]

1, 2, field effect transistors 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 1
7, 18, 19 distributed constant line 3, 10, 11, 16, 20, 21, 31 capacitor 22 input terminal 23 output terminal 24 resistance

Claims (3)

(57) [Claims] 1. A first and second field effect transistor
And an input terminal of the first field-effect transistor and a first
An input matching circuit connected between terminals, the second electric field;
Connected between the output terminal of the effect transistor and the second terminal
Output matching circuit, and the first field-effect transistor
Between an output terminal and an input terminal of the second field effect transistor
Wherein the output matching circuit is connected to the second field effect transistor.
Are connected in series between the output terminal and the second terminal.
First and second distributed constant lines, and the first and second distributed lines.
Third distributed constant having one end connected to a connection point of the cloth constant line
Having a line for at least twice the frequency of the fundamental wave
The short-circuit processing is performed, and the frequency component twice the fundamental wave is
The second field effect transistor is reflected by an output matching circuit.
Harmonic processing in which the fundamental component is superimposed by reverse injection into the output end of the
A step-matching circuit, at least the first field-effect transistor.
The output end of a transistor and the second field effect transistor
Fourth and fifth components connected in series between the input terminals of the
A cloth constant line, one end of which is the fourth and fifth distributed constant lines
And a sixth distributed constant line connected to the connection point with
Harmonic processing is also performed on the input side of the second field-effect transistor.
A semiconductor device characterized by performing a process. 2. The fourth and fifth distributed constant lines according to claim 1 , wherein
In series with the sixth distributed constant line between the connection point and ground
The semiconductor device according to claim 1, further comprising a capacitor provided so as to form a semiconductor device. 3. The other end of the sixth distributed constant line is open at the end.
2. The semiconductor device according to claim 1, wherein said semiconductor device is a semiconductor device.