JPH0918255A - Semiconductor device - Google Patents

Abstract

PURPOSE: To efficiently generate a high frequency power with limited battary capacity and voltage by approximating the power amplification efficiency of an amplifier, which requires making small-sized and light-weight, of a mobile body communication machine or the like to an ideal value obtained by the class 'E' operation as much as possible. CONSTITUTION: In the amplification circuit of FETs connected in many stages, a resonance circuit is inserted to the transmission line of an inter-stage matching circuit corresponding to the input of an FET 2 to short-circuit the harmonic components of a fundamental wave f0 . For the purpose of realizing the harmonic processing, an output matching circuit is provided with a distribution constant line which reflects harmonic components 2f0 and 3f0 by short stubs 8 and 9 respectively and inversely charges them to the drain terminal of the FET 2. Consequently, the distribution constant line 4 and a capacitor 3 provided on the gate side of the FET 2 function as a short stub for 2f0 and become a resonance circuit, thus effectively achieving the harmonic processing which improves the drain efficiency furthermore.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device which enables high efficiency amplification in the UHF band.

[0002]

2. Description of the Related Art FIG. 3 is a schematic view of "900 Megahertz Tygallium Kouritsuden Ryokuzo Fukuki" Koujitiba et al. FIG. 11 is a circuit diagram of a semiconductor device using the conventional field effect transistor (hereinafter abbreviated as FET) shown. The FETs 1 and 2 which are leased to ground have a gate terminal G, a source terminal S, and a drain terminal D, respectively. Distributed constant lines 5, 6, 22, 23, interstage matching circuit 2
2, the input matching circuit 23, the distributed constant lines 5 and 6 and the open stubs 8 and 9 form an output matching circuit.

According to this circuit, the characteristic impedance is changed by adjusting the length and width of the distributed constant lines 5, 6, 22 and 23 and the short stubs 8 and 9 with respect to the fundamental frequency f ₀ to be amplified. It has a good matching condition. Further, in the output matching circuit composed of the distributed constant lines 5 and 6 and the open stubs 8 and 9, the distributed constant line 5 and the open stub 8 cause the frequency 3f, which is three times as high as the fundamental wave, at the drain end of the FET 2.
_{At 0} , a load condition close to an infinite impedance is given, and further, due to the distributed constant lines 5 and 6 and the open stubs 8 and 9, a load condition close to a short circuit is applied at a frequency 2f _{0 that} is twice the fundamental wave. .

For this reason, frequency components which are twice or three times as high as the fundamental wave are originally unnecessary radiation, but are reflected by the output matching circuit, are back-injected into the drain terminal D of the FET 2 again, and are superimposed on the fundamental wave component. Harmonic processing is realized. Therefore, according to this circuit, a drain efficiency higher than 30% is obtained as compared with an amplifier circuit in which 2f ₀ and 3f ₀ are not processed. In UHF band power amplifiers such as mobile communication devices, which are essential to be small and lightweight, high frequency power is efficiently generated from a limited battery capacity and voltage using such a technology.

[0005]

In the circuit of the invention Problems to be Solved The conventional semiconductor device, a short circuit only by the output-side matching circuit elements for impedance matching and 2f ₀ for f _0, it is necessary to achieve a condition of opening for 3f _0, It is very difficult to achieve an ideal load condition with high accuracy, and in reality f
Matching the 2f ₀ of _0, the processing of 3f ₀ operation is forced in an incomplete state. In particular, in a FET that generates a high frequency output power of about 1 W, such as a mobile communication device, the output matching condition and the input matching condition cannot be completely independently given because the isolation between the input and the output cannot be ignored. That is, not only the load condition of the output side matching circuit, but also some kind of harmonic processing is indispensable for improving the efficiency of the input side matching circuit.

[0006]

SUMMARY OF THE INVENTION In an amplifier circuit having FETs having input / output matching circuits of a semiconductor device according to the present invention connected in multiple stages, not only the output matching circuit but also the transmission line of the input matching circuit is even-ordered. The resonance circuit is provided for short-circuiting the harmonics, especially the frequency component 2f ₀ that is twice the fundamental wave at the input terminal of the FET.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. FETs 1 and 2 are grounded to lease and have a gate terminal G, a drain terminal D, and a lease terminal S, respectively. 5, 6, 7, 8, and 9 are distributed constant lines,
Reference numerals 10 and 11 are capacitors that short-circuit 8 and 9 at high frequencies. The above elements 5, 6, 7, 8, 9, 10, 11 constitute an output matching circuit, and are connected to the drain terminal of the FET2. Further, 12, 13, 14, 15, and 3 are distributed constant lines, and 3 and 16 are capacitors that short-circuit 4 and 15, respectively. 3,4,12,13,1
Reference numerals 4 and 15 form an interstage matching circuit, that is, an input matching circuit of the FET2, and are connected between the drain terminal of the FET1 and the gate terminal of the FET2. Also 17, 18, 19
Is a distributed constant line, and 20 is a capacitor for short-circuiting 19. The above 17, 18, 19, 20 constitute an input matching circuit and are connected to the gate terminal of the FET1. 21
Is a capacitor that blocks direct current between FET1 and FET2.

The high frequency signal of frequency f ₀ supplied from the input terminal 22 of this semiconductor device is transmitted to the gate terminal G of the FET 1 with a small loss by the input matching circuit, is effectively amplified and appears at the drain terminal D. Similarly, the inter-stage matching circuit and the output matching circuit have f ₀ so as to effectively transmit a high frequency signal with a small loss or to obtain a large output power.
Are aligned against.

The distributed constant lines 5 and 6 and the capacitor 11
The short stub composed of ₃ provides a high impedance close to infinity with respect to 3f ₀ to the drain terminal of the FET 2, and the distributed constant line 5 and the capacitor 10 provide 2f ₀ with an impedance close to a short circuit. Further, among the elements forming the inter-stage matching circuit, the distributed constant line 4 and the capacitors 3 and 31 give the gate terminal of the FET 2 an impedance of which 2f ₀ is close to a short circuit.

As a result, the high frequency component generated at the output terminal 23 is reflected by the FET 2 to achieve a more ideal superposition of higher harmonics and achieve high efficiency amplification. For example, ε = 9.8
When a 900 MHz band semiconductor device is constructed using the alumina ceramic substrate of, the distributed constant line 4 has a width of 12
Even if a 1005 type chip capacitor is used by using a copper pattern having a length of 0 μm and a length of 1.85 mm, a capacitor 3 of 1000 pF and a capacitor 31 of 4 pF, a high frequency of 1.8 GHz, which is twice the fundamental wave 900 MHz, can be effectively used. Can be processed.

Here, the capacitor 3 achieves a low impedance with respect to the fundamental frequency, but is doubled to 1.8 GH.
In the vicinity of z, the influence appears as an inductor component due to the structure of the chip capacitor, so the capacitor 31 compensates for the low impedance at high frequencies.

FIG. 2 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention. In this embodiment, 1 is a FET whose source is grounded and 2 is a FET whose gate is grounded, which constitutes a cascode type amplifier circuit. The configuration and operation of the input matching circuit and the output matching circuit are the same as those of the embodiment shown in FIG. 1, but the interstage matching circuit, that is, the input circuit of the FET2 is 12, 13, 4
4 is a distributed constant line, and 4 functions as an open stub.

Generally, in a cascode type amplifier circuit, an interstage matching circuit is not provided and the FETs in the preceding and following stages are directly connected in many cases. However, in the matching circuit of this embodiment, a distributed constant line is used for the second harmonic processing. . The open stub 4 provides an impedance at the lease terminal of the FET 2 where 2f ₀ is close to a short circuit. Therefore, similar to the case of the short stub shown in the embodiment of FIG. 1, more ideal harmonic processing is achieved and high efficiency amplification is realized.

[0015]

As described above, according to the present invention, since the resonance circuit for short-circuiting even harmonics is provided in the transmission line of the input matching circuit of the FET, the fundamental wave f ₀ realized by the output side circuit is provided.
In addition to the matching of 2f _0, the short circuit of 2f ₀ , and the opening of 3f ₀ , a short circuit of 2f ₀ on the input side is realized. Therefore, it is possible to obtain a higher drain efficiency than the harmonic processing that has been achieved only under the output load condition of the FET.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional semiconductor device.

[Explanation of symbols]

1, 2 field effect transistors 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 1
7, 18, 19 Distributed constant line 3, 10, 11, 16, 20, 21, 31 Capacitor 22 Input terminal 23 Output terminal 24 Resistance

Claims (3)

[Claims] 1. In an amplifier circuit in which field effect transistors having an input matching circuit and an output matching circuit are connected in multiple stages, a transmission line of the input matching circuit of the field effect transistor has a short-circuit plane for even-order high frequencies. A semiconductor device having a resonance circuit provided for the semiconductor device. 2. A series circuit of a distributed constant line and a capacitor, which is provided to form a short-circuit plane for even-order high frequencies, is provided between the transmission line of the input matching circuit of the field effect transistor and the ground. The semiconductor device according to claim 1, wherein: 3. The transmission line of the input matching circuit of the field effect transistor has a distributed constant line with an open tip provided for forming a short-circuit surface for even harmonics. 1. The semiconductor device according to 1.