JP3224509B2 - Microwave multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave multiplier capable of achieving low spurious with a small and simple structure and capable of easily setting a frequency of a multiplied wave and a frequency to be suppressed. .

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a conventional microwave multiplier. In the drawing, reference numeral 1 denotes a multiplier circuit, and 2 denotes a buffer amplifier for amplifying a doubler output from the multiplier circuit 1 to a desired power level. The circuit 3 is provided in the multiplication circuit 1,
GaAs field effect transistor (hereinafter GaAs FE)
(Referred to as T) 5 is a fundamental wave matching circuit for inputting and outputting a signal so that the efficiency is maximized, 5 is a GaAs FET whose source is grounded, and 6 is an nth harmonic frequency output from the GaAs FET 5. An n-th harmonic matching circuit 7 for performing impedance matching on the other hand, a band-pass filter 7 for removing frequencies other than the set band and reflecting harmonics other than the fundamental frequency and the n-th harmonic to the drain terminal side of the GaAs FET 5. Reference numeral 8 denotes an n-th harmonic matching circuit provided in the buffer amplifying circuit 2 for performing impedance matching with respect to a frequency input from the band-pass filter 7. Reference numeral 9 denotes a GaAs provided in the buffer amplifying circuit 2.
FETs 10 and GaAs are provided in the buffer amplifier circuit 2.
An n-th harmonic matching circuit that performs impedance matching for the frequency output from the sFET 9, and 11 is an output terminal.

In such a conventional microwave multiplier, the GaAs FET 5 of the multiplier 1 is grounded at the source, the input side is impedance-matched to the fundamental frequency, and the output side is to the n-th harmonic. Thus, the conversion from the fundamental wave to the n-th harmonic is performed efficiently by impedance matching. Further, a band-pass filter 7 provided between the multiplication circuit 1 and the buffer amplification circuit 2 removes unnecessary waves and removes harmonics other than the fundamental wave and the desired wave.
By reflecting the light toward the drain terminal side of the AsFET 5, the conversion efficiency is further increased. The buffer amplifier circuit 2 is, similarly to the multiplier circuit 1, a GaAs source grounded GaAs.
N-harmonic matching circuit 1 for n-harmonic at input / output part of FET 9
0 is provided, and the multiplied wave output by the multiplying circuit 1 is amplified to a desired power level.

[0004]

Since the conventional microwave multiplier is configured as described above, the band-pass filter 7 provided between the multiplier 1 and the buffer amplifier 2 is used.
Has a design requirement to suppress unnecessary waves and reflect harmonics other than the fundamental wave and the desired wave to the drain terminal side of the GaAs FET 5, so that a narrow band and multi-stage bandpass filter 7 is required. When a side-coupled band-pass filter is used, it is difficult to adjust it after manufacturing, and because of the narrow band, there are large fluctuations in characteristics due to manufacturing variations such as etching accuracy, and the circuit itself becomes large. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a bias line for supplying a power supply voltage to the GaAs FETs 5 and 9 of the multiplier circuit 1 and the buffer amplifier circuit 2 is provided with an unnecessary wave suppressing function. And
In addition, a combination of a lumped-constant HPF and a distributed-constant DC cut at the output of the multiplication circuit 1 and the use of an inductor in which the n-th harmonic matching circuits 8 and 10 of the buffer amplification circuit 2 are shunt-connected to GND are used. It is another object of the present invention to obtain a microwave multiplier that can be easily adjusted.

Another object of the present invention is to provide a microwave multiplier capable of minimizing fluctuations in characteristics with respect to manufacturing errors such as etching accuracy of a printed circuit board.

[0007]

According to a first aspect of the present invention, there is provided a microwave multiplier which also functions as a bias voltage supply line.
And an even harmonic having an electrical length of 1/4 wavelength of the fundamental wave
A first tip short-circuit stub for suppressing
A fundamental wave consisting of a short-circuit inductor and capacitor
Suppressed lumped constant high-pass filter and desired multiplied wave
Formed by a coupled line having an electrical length of 1/4 wavelength of
A distributed constant DC voltage that suppresses unwanted waves other than the desired multiplied wave.
A blocking circuit and a second field effect transistor for amplifying the input waveform.
The transistor and the input side of the second field effect transistor.
And third and fourth short-circuited terminals provided on the output side.
While acting as both the inductor and the bias voltage supply line,
The 1st wavelength that has an electrical length of 1/4 wavelength of the main wave and suppresses even harmonics
And two of the leading-end short stub is obtained by example Bei.

According to a second aspect of the present invention, there is provided a microwave multiplier which also serves as a bias voltage supply line and a fundamental wave.
The first one which has an electrical length of 波長 wavelength and suppresses odd harmonics
Open-end stub and first and second short-circuited inductors
Lumped constant consisting of a capacitor and a capacitor to suppress the fundamental wave
-Type high-pass filter and a 1/4 wavelength
Other than the desired multiplied wave
Distributed constant DC voltage blocking circuit to suppress spurious waves and input
A second field-effect transistor for amplifying the generated waveform, and a second
Provided on the input and output sides of two field-effect transistors
Third and fourth tip short-circuited inductors, and vias.
電 圧 wavelength of fundamental wave
Second open-ended star for suppressing odd harmonics having an electrical length of
And the

According to a third aspect of the present invention, there is provided a microwave multiplier including a lumped constant type high-pass filter capacitor.
This is a variable capacitance capacitor.

According to a fourth aspect of the present invention, there is provided a microwave multiplier , wherein the first and second tip short-circuit stubs are provided with chip carriers.
Equipped with mounting position changing means for changing the mounting position of the pasita
Things.

According to a fifth aspect of the present invention, in the microwave multiplier , the first and second tips are provided as mounting position changing means.
A GND pattern provided so as to run in parallel with the short-circuit stub;
For conducting with the ground conductor on the back surface provided in the GND pattern
Through hole, first and second tip short-circuit stubs and G
Slide between the ND pattern and the first and second
A chip capacitor that changes the electrical length of the tip short-circuit stub
It is provided with.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a microwave multiplier according to Embodiment 1 of the present invention. In the drawing, reference numeral 15 denotes a multiplier according to Embodiment 1 of the present invention, and 16 denotes a multiplier output from the multiplier 15. A buffer amplifier circuit 3 for amplifying to a desired power level is provided in the multiplier circuit 15, and the GaAs
Fundamental matching circuits efficiency for or output the input signals so as to maximize the FET 5, GaAs FET is sourced grounded 5 (first field effect transistor
And 8 are an n-th harmonic matching circuit provided in the buffer amplifier circuit 16 to perform impedance matching with respect to an input frequency, and 9 is a GaAs provided in the buffer amplifier circuit 16.
FET (second field effect transistor) 10 is an n-th harmonic matching circuit provided in the buffer amplifier circuit 16 for performing impedance matching with respect to the frequency output from the GaAs FET 9, and 11 is an output terminal.

[0013] 21a, 21b are short-circuited stub (first and second previously having an electrical length of 1/4 wavelength of the fundamental wave f ₁
End short-circuit stubs ), 22a and 22b are short-circuit stub power supply terminals for supplying a bias voltage to the GaAs FETs 5 and 9 via the tip short-circuit stubs 21a and 21b, and 23a and 2
3b constitutes a lumped high-pass filter inductor (first and second short-circuited end inductor), 24 constitute a lumped high-pass filter Capacity data, 25
Is a DC cut (distributed constant type DC voltage blocking circuit) constituted by a coupling line having an electrical length of 1/4 wavelength of a desired multiplied wave.
Road), 26a, 26b are used in n-th wave matching circuit 8 and 10 of the buffer amplifier circuit 16 the inductor (the third and fourth
Of the short-circuited inductor ).

Next, the operation will be described. FIG. 2 shows time (a) on the horizontal axis and frequency (b) on the horizontal axis in (1) of FIG.
FIG. 3 is a waveform diagram showing a waveform when the horizontal axis in FIG. 1 (2) is time (a) and a horizontal axis is frequency (b), and FIG. 4 is a diagram. 1 (3) is a waveform diagram showing a waveform when the horizontal axis is time (a) and the horizontal axis is frequency (b). FIG. 5 is a horizontal axis showing time (a) in FIG. 1 (4). FIG. 6 is a waveform diagram showing the pass characteristics of the short-circuited stub and the lumped-constant high-pass filter of FIG. 1 when the horizontal axis represents the frequency (b). First, in the fundamental wave matching circuit 3, GaAs is applied to the fundamental wave frequency (see FIGS. 2A and 2B) inputted from the input terminal 4.
A signal is input or output so that the efficiency of the sFET 5 is maximized, and is output to the GaAs FET 5. Next, the GaAs FET 5 converts the input waveform into a multiplied wave (see FIGS. 3A and 3B) and outputs the converted waveform. Impedance anticipation of short-circuited stub 21a side from the GaAs FET 5 is open at odd harmonics of the frequency of the input frequencies including the fundamental wave f _1, since the short-circuit for even harmonics, even order Are suppressed by the tip short-circuit stub 21a.

[0015] Then, the capacitor 24 and inductor 23a, the lumped high-pass filter composed 23b, suppression of the fundamental wave f ₁ and the second harmonic is performed on the input waveform (see FIG. 6), DC-cut 25. Incidentally, suppressing the fundamental wave f ₁ by setting higher than the fundamental wave f ₁ the cut-off frequency of the lumped high-pass filter, and the fundamental wave f ₁ and the short-circuited stub 21a and lumped high-pass filter By reflecting the even-order multiplied wave to the drain terminal side of the GaAs FET 5, the conversion efficiency can be increased when this circuit is used as a multiplying circuit for obtaining the third or higher odd-order harmonics. Next, in DC cut 25,
Unnecessary waves are suppressed for the input waveform, and an inductor 26 as an input / output matching circuit of the buffer amplifier circuit 16 is used.
output to a. In the inductor 26a, the input waveform is subjected to t / N (see FIGS. 4A and 4B) and output to the GaAs FET 9. Next, GaA
Amplification is performed via the sFET 9, the inductor 26b, and the short-circuit stub 21b (see FIGS. 5A and 5B), and output from the output terminal 11.

As described above, according to the first embodiment, the short-circuiting stubs 21a and 21b having the electrical length of 1/4 wavelength of the fundamental frequency are connected to the bias lines on the output side of the multiplier circuit 15 and the buffer amplifier circuit 16. By combining this with a lumped-constant high-pass filter composed of inductors 23a and 23b and a capacitor 24 provided at the output section of the multiplier circuit 15, it is possible to obtain effects such as suppression of unnecessary waves.

Embodiment 2 FIG. FIG. 7 is a block diagram showing a microwave multiplier according to a second embodiment of the present invention, and FIG. 8 is a waveform diagram showing pass characteristics of DC cut. In FIG. 7, the same reference numerals as those in the first embodiment denote the same or corresponding parts. The description is omitted here. Embodiment 1
Bias lines on the output side of the multiplier circuit 15 and the buffer amplifier circuit 16 are connected to the short-circuit stubs 21a and 21b having an electrical length of 1/4 wavelength of the fundamental frequency, and the lumped constant high-pass provided at the output of the multiplier circuit 15. Although the combination with the filter is shown, as shown in FIG.
By providing the desired DC cuts formed by the bond line having an electrical length of a quarter wavelength of the multiplied waves (distributed constant type DC voltage blocking circuits) 32 on the output side of the multiplier circuit 15, the DC-cut 32 Due to the frequency characteristics, the multiplied wave frequency f ₁₁
Effects such as can be suppressed harmonics f ₁₂ and f ₁₃ other than is obtained.

Embodiment 3 FIG. 9 is a configuration diagram showing a microwave multiplier according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in Embodiment 1 denote the same or corresponding parts, and a description thereof will be omitted.
35 is a multiplier circuit according to the third embodiment of the present invention, 36 is a buffer amplifier circuit according to the third embodiment of the present invention, 41
Reference numerals a and 41b denote open-end stubs ( first and second open-end stubs) each having an electrical length of １ ／ wavelength of the fundamental frequency.
B ), 42a and 42b are open end stubs 41a and 41b.
Is an open stub power supply terminal for supplying a bias voltage to the GaAs FETs 5 and 9 via. In the first embodiment, G
aAsFETs 5 and 9 have tip short-circuit stubs 21a and 21b.
Are shown, but as shown in FIG. 9, the stubs 41 with open ends are attached to the GaAs FETs 5 and 9.
a and 41b may be connected.

[0019] In this case, impedance anticipation of open stub 41a side from the GaAs FET 5 is open at short circuit the odd harmonics of the frequency of the input frequencies including the fundamental wave f _1, with respect to even-order harmonics Therefore, odd-order harmonics are suppressed by the open-end stub 41a. On the other hand, the fundamental wave f ₁ is further suppressed by the lumped constant type high-pass filter composed of the capacitor 24 and the inductors 23 a and 23 b, and the fundamental wave f ₁ and the odd-order multiplied wave are reflected to the drain terminal side of the GaAs FET 5. Thus, when this circuit is used as a multiplier circuit 35 for obtaining even-order harmonics of second or higher order, effects such as an increase in conversion efficiency can be obtained.

FIG. 10 is a waveform diagram showing characteristics when an inductor is used in the input / output matching circuit of the buffer amplifier circuit. As shown in the figure, the input / output matching circuit of the buffer amplifier circuit 36 is connected to GND. By using inductors 26a and 26b shunt-connected to each other, as shown in FIG. 10, it is possible to suppress unnecessary gain at frequencies other than the desired frequency, as compared with a matching circuit using an open-end stub 41b. And the like.

Embodiment 4 FIG. FIG. 11 is a configuration diagram showing a multiplier circuit of a microwave multiplier according to a fourth embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment denote the same or corresponding parts, and a description thereof will be omitted. In the first embodiment, the capacitor 24 constituting the lumped-constant high-pass filter provided at the output section of the multiplication circuit 15 cannot be varied. However, as shown in FIG. Thus, the cutoff frequency of the lumped-constant high-pass filter can be adjusted, and the amount of suppression of unnecessary waves at the output of the multiplier can be varied.

Embodiment 5 FIG. 12 is a configuration diagram showing a circuit pattern for changing the electrical length of the tip short-circuit stub according to the fifth embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment denote the same or corresponding parts, and a description thereof will not be repeated. 51 is a multiplier circuit 15
A GND pattern (attachment position changing means) provided so as to run in parallel with the tip short-circuit stubs 21a and 21b provided in the buffer amplifier circuit 16;
Through holes (attachment position variable means) for conducting with the ground conductor on the back surface provided in
These are chip capacitors (attachment position varying means) for cutting DC between the a and 21b and the ground conductor. In the fifth embodiment, as shown in the figure, the chip capacitor 53 is slid between the tip short-circuit stub 21a and the GND pattern 51, and the electrical length of the tip short-circuit stub 21a is changed. The effect is obtained such that adjustment can be easily performed without pattern cutting or component replacement.

[0023]

As described above, according to the first aspect of the present invention , the fundamental wave can be used as a bias voltage supply line.
The first having an electrical length of 1/4 wavelength of and suppressing even harmonics
A tip short-circuit stub and first and second tip short-circuit inductors
Lumped constant consisting of a capacitor and a capacitor to suppress the fundamental wave
-Type high-pass filter and a 1/4 wavelength
Other than the desired multiplied wave
Distributed constant DC voltage blocking circuit to suppress spurious waves and input
A second field-effect transistor for amplifying the generated waveform, and a second
Provided on the input and output sides of two field-effect transistors
Third and fourth tip short-circuited inductors, and vias.
電 圧 wavelength of fundamental wave
Second short-circuiting star having an electrical length of and suppressing even harmonics
Frequency band so that unnecessary frequency bands are suppressed.
Pressure can be reduced, miniaturization and easy adjustment
There is.

According to the second aspect of the present invention, the bias voltage
供給 wavelength of the fundamental wave
First open-end stub having long air and suppressing odd harmonics
And first and second tip short-circuit inductors and capacitors.
A lumped constant high-pass filter made of Sita that suppresses the fundamental wave
Filter having an electrical length of 1/4 wavelength of the desired multiplied wave.
Suppress unnecessary waves other than the desired multiplied wave formed by a combined line
Distributed constant DC voltage blocking circuit and amplified input waveform
A second field-effect transistor, and a second field-effect transistor .
3rd and 4th transistors provided on the input and output sides of the transistor
And fourth tip short-circuit inductor and bias voltage supply line
And has an electrical length of 1/4 wavelength of the fundamental wave
And a second open-end stub for suppressing odd harmonics.
With this configuration, unnecessary frequency bands can be suppressed.
In addition, there is an effect that the size can be reduced and the adjustment can be easily performed.

According to the third aspect of the present invention, the lumped constant type
The capacitor of the high-pass filter is replaced with a variable capacitor
The order of harmonics to be suppressed and
There is an effect that the suppression level can be made variable.

According to the fourth aspect of the present invention, the first and the second
Attach the chip capacitor to the second tip short-circuit stub
It is configured to have a mounting position changing means for changing the
The order of the harmonics to be suppressed and the suppression level are variable.
Can be manufactured, such as etching accuracy of printed circuit boards
Variations in characteristics can be reduced even for manufacturing errors.
There is a clear effect.

According to the fifth aspect of the present invention, the mounting position is possible.
Parallel running with the first and second tip short-circuit stubs as a variant
To a GND pattern and a GND pattern
A through hole for conduction with the ground conductor on the rear surface provided,
Between the first and second tip short-circuit stubs and the GND pattern;
Slide between the first and second tip shorting stubs.
With a chip capacitor that changes the electrical length
The order of harmonics to be suppressed and the suppression level
Can be variable, etching of printed circuit board
Reduce fluctuations in characteristics even with manufacturing errors such as accuracy.
There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a microwave multiplier according to Embodiment 1 of the present invention.

FIG. 2 is a waveform diagram showing a waveform when the horizontal axis in FIG. 1A is time (a) and the horizontal axis is frequency (b).

FIG. 3 is a waveform diagram showing waveforms when the horizontal axis in FIG. 1 (2) is time (a) and the horizontal axis is frequency (b).

FIG. 4 is a waveform diagram showing a waveform when the horizontal axis in FIG. 1 (3) is time (a) and the horizontal axis is frequency (b).

FIG. 5 is a waveform diagram showing waveforms when the horizontal axis in FIG. 1 (4) is time (a) and the horizontal axis is frequency (b).

FIG. 6 is a waveform chart showing pass characteristics of the short-circuit stub and the lumped-constant high-pass filter of FIG. 1;

FIG. 7 is a configuration diagram illustrating a microwave multiplier according to a second embodiment of the present invention.

FIG. 8 is a waveform diagram showing pass characteristics of a DC cut.

FIG. 9 is a configuration diagram showing a microwave multiplier according to a third embodiment of the present invention.

FIG. 10 is a waveform chart showing characteristics when an inductor is used in an input / output matching circuit of a buffer amplifier circuit.

FIG. 11 is a configuration diagram showing a multiplier circuit of a microwave multiplier according to a fourth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a circuit pattern for changing the electrical length of a short-circuited stub according to a fifth embodiment of the present invention.

FIG. 13 is a configuration diagram showing a conventional microwave multiplier.

[Explanation of symbols]

3 fundamental matching circuits, 5,9 GaAs FET (first
And a second field-effect transistor), a 15-multiplier circuit, a 16-buffer amplifier circuit, 21a and 21b tip short-circuit stubs ( first and second short-circuit stubs ), 23a,
23b Inductor ( First and second tip short-circuited inductors)
Kuta), 24 Capacity data, 25,32DC cut (distributed constant type DC voltage blocking circuits) 26a, 26b inductor
(Third and fourth tip short-circuit inductors), 41
a, 41b Open-end stubs ( first and second open-end stubs)
Discharge stub ), 46 variable capacitance capacitors, 51 GND
Pattern (attachment position varying means), 52 through hole (attachment position varying means), 53 chip capacitor (attachment position varying means).

Continuation of front page (56) References JP-A-1-236705 (JP, A) JP-A-7-245501 (JP, A) JP-A-62-21111 (JP, A) JP-A-5-304419 (JP, A) JP-A-7-66656 (JP, A) JP-A-6-106442 (JP, A) JP-A-2-76401 (JP, A) JP-A-2-179101 (JP, A) 4-114215 (JP, U) JP-A 4-107904 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03B 19/00-19/18

Claims (5)

(57) [Claims] (1)Provided after the fundamental wave matching circuit,
First field-effect transistor for generating a harmonic of a wave
And The first field effect transistor is provided at a stage subsequent to the first field effect transistor.
Also serves as the ias voltage supply line, and is 1/4 of the fundamental wave
1st tip short circuit which has electric length of wavelength and suppresses even harmonics
A stub, The first and second short-circuit stubs are provided after the first short-circuit stub,
And a second tip short-circuit inductor and a capacitor.
A lumped constant high-pass filter for suppressing the fundamental wave, It is provided after the lumped constant type high-pass filter.
A coupling line having an electrical length of 1/4 wavelength of the desired multiplied wave.
Distribution constant that suppresses undesired waves other than the desired multiplied wave
DC voltage blocking circuit, Provided after the distributed constant DC voltage blocking circuit,
A second field effect transistor for amplifying the applied waveform; Input and output sides of the second field effect transistor
A third and a fourth tip short-circuit inductor provided in The second field effect transistor is provided after the second field effect transistor.
Also serves as the ias voltage supply line, and is 1/4 of the fundamental wave
2nd tip short circuit which has electric length of wavelength and suppresses even harmonics
A microwave multiplier having a stub. (2)Provided after the fundamental wave matching circuit,
First field-effect transistor for generating a harmonic of a wave
And The first field effect transistor is provided at a stage subsequent to the first field effect transistor.
Also serves as the ias voltage supply line, and is 1/4 of the fundamental wave
First open end with electrical length of wavelength to suppress odd harmonics
A stub, The stub is provided after the first open end stub,
And a second tip short-circuit inductor and a capacitor.
A lumped constant high-pass filter for suppressing the fundamental wave, It is provided after the lumped constant type high-pass filter.
A coupling line having an electrical length of 1/4 wavelength of the desired multiplied wave.
Distribution constant that suppresses undesired waves other than the desired multiplied wave
DC voltage blocking circuit, Provided after the distributed constant DC voltage blocking circuit,
A second field effect transistor for amplifying the applied waveform; Input and output sides of the second field effect transistor
A third and a fourth tip short-circuit inductor provided in The second field effect transistor is provided after the second field effect transistor.
Also serves as the ias voltage supply line, and is 1/4 of the fundamental wave
Open second end that has electrical length of wavelength and suppresses odd harmonics
A microwave multiplier having a stub. 3. A capacitor of lumped high-pass filter, wherein, which is a variable capacitor
The microwave multiplier according to claim 1 or 2 . 4. The microwave multiplier according to claim 1, wherein said first and second short-circuit stubs have mounting position changing means for changing the mounting position of the chip capacitor. 5. A mounting position varying means, comprising: a GND pattern provided so as to run in parallel with the first and second tip short-circuiting stubs; and a through hole provided in the GND pattern for conducting with a ground conductor on a back surface. Sliding between the first and second tip short-circuit stubs and the GND pattern, the first and second tip
5. The microwave multiplier according to claim 4, further comprising: a chip capacitor for changing an electrical length of the short-circuit stub .