JPS633225Y2 - - Google Patents
Info
- Publication number
- JPS633225Y2 JPS633225Y2 JP2231082U JP2231082U JPS633225Y2 JP S633225 Y2 JPS633225 Y2 JP S633225Y2 JP 2231082 U JP2231082 U JP 2231082U JP 2231082 U JP2231082 U JP 2231082U JP S633225 Y2 JPS633225 Y2 JP S633225Y2
- Authority
- JP
- Japan
- Prior art keywords
- hybrid
- amplifier
- balanced
- balanced amplifier
- output side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003111 delayed effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Microwave Amplifiers (AREA)
- Amplifiers (AREA)
Description
【考案の詳細な説明】
本考案は、マイクロ波帯のトランジスタを使用
したバランス形増幅器に関する。[Detailed Description of the Invention] The present invention relates to a balanced amplifier using microwave band transistors.
バイポーラトランジスタやFETを使用したマ
イクロ波帯の低雑音増幅器は、増幅器の雑音特性
を最良に調整すると増幅器の入力回路の整合が大
きく外れる為、増幅器が安定に動作しないことが
考えられる。このような問題を解決する為に、従
来、第１図に示すようにバランス形増幅回路が使
用されている。この増幅回路の動作は、信号入力
端Ａから入つた信号は、入力側にある90゜3dBハ
イブリツド１により、増幅器３へ振幅１／√２位
相が90゜遅れて加わり、増幅器４へは振幅１／√
２位相0゜で供給されて各々の増幅器（単位増幅
器）で増幅された後、出力側の90゜3dBハイブリ
ツド２によつて増幅器４からの出力は位相が90゜
遅れ、増幅器３からの出力は位相0゜で合成され
る。この時、増幅器３，４の増幅利得が等しけれ
ば信号出力端Ｂでは増幅信号は同相合成され、バ
ランス形増幅器の増幅利得は、単位増幅器の利得
と同じになる。一方、信号入力端Ａまたは信号出
力端Ｂから増幅器を見た端子インピーダンスとの
不整合による反射は、増幅器端面での反射位相お
よび振幅が等しければ、ハイブリツドの吸収抵抗
に反射電力がすべて吸収されるので、信号入出力
端子の整合は良好に保たれる。即ち、バランス形
増幅器において、最適の雑音特性を保ちつつ良好
な入出力インピーダンス整合を得るには、90゜位
相差と3dB結合度の周波数特性がこの値からいか
にずれないように構成するかにかかつている。従
来のハイブリツドにブランチライン形を使用した
場合には、形状が大きくなつたり、インピーダン
ス整合が良好な周波数帯域が狭くなつたりして入
力端子をブランチングフイルタに直結した場合に
安定な特性を得られない欠点があつた。一方、イ
ンタデイジタル形ハイブリツドは、小型の形状に
て結合度、位相差ともに良好な特性を示すが、ハ
イブリツドの構造が複雑な為、製造上の歩留りが
悪かつたり微細パターンとなるため他の回路と一
緒に同一基板上に構成することが出来ず、インタ
ーデイジタル型ハイブリツドを用いた場合には、
寸法、性能とも良好になるにもかかわらず、高価
になる欠点があつた。 Microwave band low-noise amplifiers that use bipolar transistors or FETs may not operate stably because the matching of the amplifier's input circuit will be significantly off when the amplifier's noise characteristics are optimally adjusted. In order to solve such problems, a balanced amplifier circuit as shown in FIG. 1 has conventionally been used. The operation of this amplifier circuit is such that the signal input from the signal input terminal A is applied to the amplifier 3 with an amplitude of 1/√2 phase delayed by 90° due to the 90° 3dB hybrid 1 on the input side, and the signal is applied to the amplifier 4 with an amplitude of 1/√2 phase delayed by 90°. /√
After being supplied with two phases of 0° and amplified by each amplifier (unit amplifier), the output from amplifier 4 is delayed by 90° in phase due to the 90° 3dB hybrid 2 on the output side, and the output from amplifier 3 is Combined with a phase of 0°. At this time, if the amplification gains of the amplifiers 3 and 4 are equal, the amplified signals are in-phase combined at the signal output terminal B, and the amplification gain of the balanced amplifier becomes the same as the gain of the unitary amplifier. On the other hand, for reflections due to mismatching with the terminal impedance when looking at the amplifier from signal input terminal A or signal output terminal B, if the reflection phase and amplitude at the amplifier end face are equal, all of the reflected power will be absorbed by the hybrid absorption resistor. Therefore, good matching between signal input and output terminals is maintained. In other words, in order to obtain good input/output impedance matching while maintaining optimal noise characteristics in a balanced amplifier, it is important to configure the amplifier so that the frequency characteristics of 90° phase difference and 3 dB coupling do not deviate from these values. There used to be. When using a branch line type in a conventional hybrid, the shape becomes larger and the frequency band where impedance matching is good becomes narrower, making it difficult to obtain stable characteristics when the input terminal is directly connected to a branching filter. It had some flaws. On the other hand, interdigital hybrids are small in size and exhibit good characteristics in terms of both coupling degree and phase difference, but because the hybrid structure is complex, manufacturing yields are poor and fine patterns are required, making it difficult to use other circuits. If an interdigital hybrid is used and cannot be configured on the same board with
Although it had better dimensions and performance, it had the disadvantage of being more expensive.
本考案の目的は、従来のこのような欠点を解消
し、安価で広帯域のバランス形増幅器を提供する
ことにある。 An object of the present invention is to eliminate these conventional drawbacks and provide an inexpensive, broadband balanced amplifier.
この目的のために本考案に係るバランス形増幅
器は、２個の高周波トランジスタ増幅器と、入力
側90゜3dBハイブリツドと出力側90゜3dBハイブリ
ツドからなるバランス形増幅器において、前記入
力側ハイブリツドとしてインタデイジタル形90゜
ハイブリツドを、前記出力側ハイブリツドとして
ブランチライン形90゜3dBハイブリツドをそれぞ
れ設けたことを特徴とするものである。 For this purpose, the balanced amplifier according to the present invention is a balanced amplifier consisting of two high-frequency transistor amplifiers, a 90° 3 dB hybrid on the input side and a 90° 3 dB hybrid on the output side. The present invention is characterized in that a branch line type 90° 3 dB hybrid is provided as the output side hybrid.
次に、本考案によるバランス形増幅器の構成を
実施例について説明する。 Next, an embodiment of the configuration of a balanced amplifier according to the present invention will be described.
第１図のバランス形増幅器に於て、入力側ハイ
ブリツド１にインターデイジタル形90゜3dB方向
性結合器を、出力側ハイブリツド２にブランチラ
イン形90゜3dB方向性結合器を、それぞれ使用す
ることにより、雑音特性を最適に保ちつつ、入力
インピーダンスを広帯域に良好に出来、一方構成
例第２図ａに示すように単位増幅器７，８と出力
側ハイブリツド６を同一基板上に構成したり、第
２図ｂのように単位増幅器７，８、出力側ハイブ
リツド６、次段増幅器９を同一基板に構成し、こ
れによつて安価な増幅器を得ることが出来る。 In the balanced amplifier shown in Figure 1, by using an interdigital type 90° 3dB directional coupler for the input side hybrid 1 and a branch line type 90° 3dB directional coupler for the output side hybrid 2. , the input impedance can be made good over a wide band while keeping the noise characteristics optimal. On the other hand, as shown in FIG. As shown in FIG. b, the unit amplifiers 7 and 8, the output side hybrid 6, and the next stage amplifier 9 are constructed on the same substrate, thereby making it possible to obtain an inexpensive amplifier.
第１図はバランス形増幅器の回路構成図、第２
図は本考案によるバランス型増幅器の回路構成例
を示す図である。
１……入力側90゜3dBハイブリツド、２……出
力側90゜3dBハイブリツド、３，４……単位増幅
器、５……インターデイジタル型90゜3dBハイブ
リツド、６……ブランチライン型90゜3dBハイブ
リツド、７，８……単位増幅器、９……次段増幅
器。
Figure 1 is a circuit diagram of a balanced amplifier, Figure 2 is a circuit diagram of a balanced amplifier.
The figure is a diagram showing an example of the circuit configuration of a balanced amplifier according to the present invention. 1... Input side 90° 3dB hybrid, 2... Output side 90° 3dB hybrid, 3, 4... Unit amplifier, 5... Interdigital type 90° 3dB hybrid, 6... Branch line type 90° 3dB hybrid, 7, 8...Unit amplifier, 9...Next stage amplifier.
Claims (1)
90゜3dBハイブリツドと出力側90゜3dBハイブリツ
ドからなるバランス形増幅器において、前記入力
側ハイブリツドとしてインタデイジタル形90゜ハ
イブリツドを、前記出力側ハイブリツドとしてブ
ランチライン形90゜3dBハイブリツドをそれぞれ
設けたことを特徴とするバランス形増幅器。 Two high frequency transistor amplifiers and input side
A balanced amplifier consisting of a 90° 3dB hybrid and an output side 90° 3dB hybrid, characterized in that an interdigital type 90° hybrid is provided as the input side hybrid, and a branch line type 90° 3dB hybrid is provided as the output side hybrid. Balanced amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2231082U JPS58125411U (en) | 1982-02-19 | 1982-02-19 | balanced amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2231082U JPS58125411U (en) | 1982-02-19 | 1982-02-19 | balanced amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58125411U JPS58125411U (en) | 1983-08-26 |
| JPS633225Y2 true JPS633225Y2 (en) | 1988-01-27 |
Family
ID=30034399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2231082U Granted JPS58125411U (en) | 1982-02-19 | 1982-02-19 | balanced amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58125411U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004506368A (en) * | 2000-08-07 | 2004-02-26 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Noise and input impedance matching amplifier |
| WO2011004419A1 (en) * | 2009-07-06 | 2011-01-13 | 株式会社 東芝 | Directional coupler |
-
1982
- 1982-02-19 JP JP2231082U patent/JPS58125411U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58125411U (en) | 1983-08-26 |
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