JPS6110323A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To obtain an analog output shaken around a desired midpoint with simple constitution by connecting an output of a linear D/A converting section at an input terminal of an index D/A converting section and providing a midpoint bias terminal at the index D/A converting section. CONSTITUTION:A linear D/A converting section 10 is provided with input buffers BF0-BF9 and an output of the buffers is inputted to a resistance ladder network LAn. A reference bias terminal 14 is connected to the least significant bit of the ladder network LAn. The index D/A converting section 12 is provided with the resistance ladder network LA0 and a midpoint bias potential VM is given.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter equipped with a linear DA converter and an index DA converter each having an R-2R type resistance ladder network.
The configuration is simplified by directly connecting the A conversion section and providing a midpoint/2-Ias terminal to the index DA conversion section.

Conventionally, this type of digital-to-analog converter is
A circuit configuration as shown in FIG. 1 has been proposed.

The circuit shown in FIG. 1 includes a linear DA converter 10, an operational amplifier OP, and an exponential DA converter 12.

+7 In the near DA converter 10, human buffers BFo-BF9 are provided which respond to the 10-bit signals of the digital input IN, and the output signals of these input buffers are processed by two types of resistors with a resistance ratio of 1:2. Rn and 2Rn f are arranged to be inputted into an R-2R type resistor ladder network LAnK connected in a ladder shape. The input capacitors BFo to BF are all set at a relatively high reference potential VDD (="H") by the analog switch As that responds to the l-bit signal INIK of the digital long sword IN, as shown in FIG.
) or a circuit equivalent to a circuit BF that switches a relatively low reference potential vss (==: "L"), for example, when the signal INI is 6
1” is VDDY.

Select each resistance ladder network LA
supply to n.

A reference bias terminal 14 for applying a reference bias potential VT' is connected to the terminal end of the lowest pin (LSB)@1 of the resistance ladder network LAn via a terminal resistor 2Rnf. For example, for the standard 2 Iasumi level vT,
ss (which may also be at ground potential) is applied.

The analog output extracted from the most significant bit (MsB) 111 of the resistance ladder network LAn is the digital large NIC.
It is proportional and is supplied to the inverting input of the operational amplifier oP. The non-inverting input terminal of the operational amplifier oP has a midpoint and
A midpoint bias potential VM for determining the center of the swing of the analog output from the operational amplifier OP is applied to the terminal 16.

The index DA converter 12 is provided with two types of resistors RQ with a resistance ratio of 1:2 and an R-2R type resistor ladder network U that is assembled in a 2ROY ladder shape. , the midpoint/minus potential VM is given from the midpoint/reas terminal 16, and the operational amplifier O
Analog outputs centered on P to 7M can be input.

In the above circuit, if you want the analog output to swing around an appropriate voltage value, you can set the midpoint bias potential "6tt" as appropriate.For example, if you set The center is mostly CvDD+
It swings around Vss)/2'.

The resistor ladder network LAG is provided to generate an output of 1/2N (where N is 0, 1, 2, etc.) of the analog output from the amplifier oP. These outputs are controlled by analog switches ASi,
ASi-1----AS1, is selectively selected by ASOK and outputs an analog output vOU to the analog output terminal 18.
It is set to K so that it can be sent out as T.

The digital-to-analog converter described above is capable of DA converting digital data including exponent bits and mantissa bits, but it converts the output of the linear DA converter (mantissa DA converter) 10 into an exponential DA converter via an operational amplifier OPY. Since the signal is supplied to a criminal, it is affected by the offset error of the operational amplifier, settling time, etc., and has the drawbacks of low DA conversion accuracy. In addition, the temperature characteristics are not good,
It also has drawbacks such as difficulty in high-speed conversion.

By the way, as the above-mentioned type of digital-to-analog converter, one having a circuit configuration as shown in FIG. 3 has also been proposed.

The difference between the circuit in Figure 3 and the circuit in Figure 1 is that the circuit in Figure 3 is
The output terminal of the IJ near DA conversion section 10 is directly connected to the input terminal of the index DA conversion section, and secondly, the output terminal of the near DA conversion section 10 is directly connected to the input terminal of the index DA conversion section 1.
2 resistor ladder network LAG has R and 2RO for each parallel resistance (1tRo/2 and Ro for the terminal part)
Y is added as shown in the figure to form an R-2R T-type circuit T, and by applying the reference voltage VDD and '/ss 'l to each T-type circuit from the terminal field and η, it is effectively possible to obtain (VDD+V
The aim is to achieve the midpoint of 8S)/2.

According to the configuration shown in Figure 3, are there any disadvantages associated with using an operational amplifier?
It can be removed, but new RQ, 2RQ, RO/2
Since this resistor is added, the number of elements increases, the degree of integration decreases when integrated into an IC, and the conversion speed slows down due to an increase in capacitance with the substrate. Furthermore, there is also the drawback that current bias tends to occur due to resistance value errors between the T-shaped circuits, resulting in a reduction in conversion accuracy.

This invention has been made to eliminate the drawbacks of the above-mentioned prior art. yal-characterized.

FIG. 4 shows the circuit configuration of a digital-to-analog converter according to an embodiment of the present invention, and similar parts to those in FIG. 1 or 3 are given the same reference numerals and detailed explanations are omitted. do.

The characteristics of the circuit shown in FIG. 4 are that the output terminal of the resistance ladder network LAn of the linear DA converter 10 is directly connected to the input terminal of the resistance ladder network LAG of the exponential DAA converter 12, and the parallel resistance ( A midpoint bias terminal 16 is provided in common to 2Ro and RQ of the terminal part, and a midpoint bias terminal 16 is provided to this terminal 16.
The reason for this is that the voltage is applied to the IASUMI position. In this case - as an example, VM is (VDD+VSS)/2 and vT is vss, VDD or (VDD+V88)/2
It can be either special Kv7yt (VD
D + VSS ) /2 has the advantage that harmonic distortion can be minimized when a sine wave is generated as the analog output vou'r.

According to the configuration shown in Figure 4, no operational amplifier is used, so
It is not affected by offset errors, settling time, etc. Furthermore, compared to the circuit shown in FIG. 3, the number of elements is smaller, the degree of integration is improved, and the stray capacitance is also smaller, so high-speed conversion is possible.

Moreover, high conversion accuracy is obtained without the current bias as described in connection with FIG.

As described above, according to the present invention, in a digital-to-analog converter having a linear DA conversion section and an index DA conversion section, the output terminal of the IJ near DA conversion section is connected to the index DA conversion section.
Since it is directly connected to the input terminal of the A converter and also provided with a midpoint bias terminal in the index DAA converter, an analog output that can be centered on the desired midpoint based on digital data including the mantissa and exponent parts can be generated using a simple circuit. In addition to the configuration, it is possible to obtain the effect of significantly improving conversion accuracy, conversion speed, degree of integration, temperature characteristics, etc.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a conventional digital-to-analog converter; Fig. 2 is an equivalent circuit diagram of the input buffer in Fig. 1; and Fig. 3 is a circuit diagram showing an example of a conventional digital-to-analog converter. Exemplary Circuit Diagram FIG. 4 is a circuit diagram of a digital-to-analog converter according to an embodiment of the present invention. 10... Linear DA converter, 12... Exponential DAA converter, 16... Center/earth terminal, 18... Analog output terminal, LAn, LAO-R-2R type resistor network, As . ASQ 5-ASi...Analog switch.

Claims (1)

[Claims] A signal corresponding to a plurality of bits of digital input is
- the first R by inputting into the 2R type resistor ladder network;
- A linear DA converter that extracts an analog output proportional to the digital input from a 2R type resistor ladder network; -1/2^N of the analog output from the 2R type resistor ladder network (N is 1, 2
, 3, etc.), the output end of the linear DA converter is connected to the A midpoint bias terminal is provided that is directly connected to the input terminal of the exponential DA converter and is common to the parallel resistances of the second R-2R type resistor network, and the center of the swing of the analog output is determined at this midpoint bias terminal. A digital-to-analog converter characterized in that a midpoint bias potential is applied.