JPS5860821A - Digital to analog converting and output equipment - Google Patents

Abstract

PURPOSE:To perform digital-to-analog conversion through a less-bit converter by grouping digital signals in such a way that they overlap, and D/A-converting the groups of bits according to the position of the most significant digit bit. CONSTITUTION:A digital signal of (m)-bit constitution (e.g. 14 bits) outputted from digital equipment is shifted by a prescribed number of bits from the least significant digit bit to obtain groups of (n) bits (e.g. eight bits) which overlap mutually; and the most significant digit bit having a logical value ''1'' is detected among the high-order digit bits except (n) bits in the least significant digit group at parts 9-14 and on the basis of the position of the most significant digit bit, one of those groups of bits is converted into an analog signal by an (n)-bit D/A converter 1. Then, the analog signal is amplified at a part 3 with prescribed magnification. Consequently, the digital signal of (m)-bit constitution is converted into the analog signal by the (n)-bit D/A converter of less- bit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-7' Narok conversion output device used particularly in the field of measuring instruments and the like.

To connect the output of a digital device to an analog recorder or the like, the digital output is usually converted to obtain an analog output. In that case, according to this method, the analog output changes stepwise, so if the digital output is output in 12 bits, a 12-bit converter is used to keep the resolution the same. However, as the resolution of digital equipment is improved, the number of bits of the converter also increases, making it extremely expensive. Additionally, D/A converters generally consist of a current adder that includes multiple resistors, and weighting is done based on the resistance values, so this is especially true for multi-pin L-D/A converters. Resistance accuracy with higher bit order is required.

Therefore, an object of the present invention is to provide a digital-to-analog conversion output device capable of converting a digital signal into an analog signal and outputting it using a D/A converter having a smaller number of bits than the number of output hits of a technical equipment. It's about doing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS -1 This invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

In this embodiment, a 14-hit digital signal output from a digital rotation speed measuring device is processed by an 8-hit θ/A converter, and the rotation speed is adjusted from 30rllll to 100,0
This is an output device for analog display in the range of 0 Orllll, in which case the measurement range has the following two range configuration.

The output side of this D/A converter 1 has the aforementioned L range.
An H range selector switch 2' is connected.

This selector switch 2 has a fixed contact a on the L range side and a fixed contact A on the H range side, and the analog signal switched by these is amplified by an operational amplifier 3 and then output terminal 4.
The signal is applied to an analog display (not shown) via. In this case, the operational amplifier 3 has four resistors ~R4 connected in parallel to each other in order to multiply its output by a predetermined time, in this embodiment by 4 degrees (n = an integer from 0 to 3). There is. Each resistance R
1 to IL4 are selected by analog switches 8W1 to SW4 controlled by a gain control signal described later, and R
1 when 1, 4 times when R2, 16 times when R3, R
When the number is 4, each multiplier (kein) of 64 times can be obtained.

On the other hand, the digital output from a digital rotation speed measuring device (not shown) is d. - d13, and each of these hits is input into the 1)/A converter 1 via the first to fourth gate circuits 5 to 8 in groups of 8 hits. That is, in this embodiment, when the first gate circuit 5 is on, d. - d7 are input to the D/A converter 1, and similarly, when the second gate circuit 6 is on, d2 to d0, and when the third gate circuit 7 is on, d4 to dlls are input to the D/A converter l. When the gate circuit 8 is on, eight bits, such as bits d6 to d13, are input to the D/A converter 1. Further, this digital-to-analog conversion output device includes an OR circuit 9 for calculating the logical sum of the ninth hit d8 and the tenth hit d9, and an eleventh hit
Bit dl.

and the 12th hit) (OR circuit 1 that takes the logical sum with 'I+
An OR circuit 11 is provided which calculates the logical sum of the 0 and 13th bits a, . . . and the 14th bit d13. In this case, the output side of the Oat circuit 10 is connected to a switch element 12 that operates depending on the output state of the OR circuit II, and the output side of the OR circuit 9 is connected to the switch element 12, which is the same as the switch element 12 (the output state of the 011 circuit 11). A switch element 13 operated by the switch element 13 and a switch element 14 operated by the signal output from the OR circuit !0 when the switch element 12 is on are connected in series.In reality, each of these switches 12 to 14 can be easily configured by using 3-state]1 software γ etc.The above-mentioned OR
The output terminals of the circuit 11 and the switch elements 12 and 14 are connected to the input terminals of a three-person type NOR circuit 15, and the output terminal thereof is connected to the first gate circuit 5♂ analog switch SWI. There is.

Further, the output terminal of the switch element 14 is connected to the second gate circuit 6 and the analog switch SW2, and similarly the output terminal of the switch element 12 is connected to the third gate circuit 7 and the analog switch SW3. The output terminal of is connected to the fourth gate circuit 8 and the analog switch 8W4.

Next, the operation of this invention will be explained. In the digital-to-analog conversion output device shown in this example,
8th human d? It is determined whether any of the higher order bits d8 to d13 contains the logical value I, and the following operation is performed accordingly. That is, if none of the 9th bit d8 to the 14th bit 1"+3 contains a logic value of 1, the output of each OR circuit 9 to 11 is 0", and therefore the output from the N OIt circuit 15 is 1'' is output. This output turns on the first gate circuit 5 and is also applied as a gain control signal to the analog switch SWI, turning it on. This causes the least significant bit d.

~Each logical value at the 8th bit d1 is the first gate circuit 5
The signal is input to the D/A converter 1 via the D/A converter 1 and converted into an analog signal. Then, this analog signal appears at the output terminal 4 via the arithmetic amplification circuit 3 whose amplification rate is set to 1 by turning on the L level-H level changeover switch 2 and the analog switch SWI. Accordingly, if the logical values of each of d6 to d7 are all 1, then 255 mV or 25.5 mV will be applied to the output terminal 4 by switching the switch 2.
mV is output. Next, the 11th bit d. ~14th
Each logical value of bit d13 is 0, but the ninth bit ds
Assuming that the logical value of either or both of and the tenth hit d contains 1, the output of the OR circuit 9 is “
In this case, since the switch elements 13 and 14 are both in the ON state, the output of the NOR circuit 15 is inverted by the output signal and becomes 0°, and the first gate circuit 5 is turned on. The output of the OR circuit 9 is applied as a gain control signal to the analog switch SW2, so the analog switches SWI and SW2 alternate. 8W2 is turned on, and the amplification rate of the operational amplifier 3° becomes 4.

As a result, each logical value from the second hit d2 to the tenth hit d is transmitted to the D/A converter 1 via the second gate circuit 6.
is input and converted into an analog signal. This analog signal is then sent to the operational amplifier 3 via the switch 2, where it is amplified four times and then output to the output terminal 4. Note that the minimum value when the second gate circuit 6 and analog switch SW2 are turned on by the output from the OR circuit 9 is that the logical value from d9 to d2 is [01000
000,J, while the maximum value is "11111111". In other words, if these digital values are converted to analog values and multiplied by 4, the result will be 256 m in the L range.
V~-10102O, 25.6m at H1Z
The output voltage is V~'102.0 mV. Then, the 10th hit d exceeds this maximum value. When the logical value of either or both of the dll of the 12th hit becomes 1, the output of the OR circuit 1f) becomes '1'. in this case,
Since the switch element 12 is in the on state, its output "1"
'' indicates the switch element 14, the third gate circuit 7 and N
OI4 circuit] 5 and is also applied as a gain control signal to the analog switch 8W3.

As a result, the switch element 14 is turned off and the OR is performed.

The second gate circuit 6 and analog switch SW2 are turned off regardless of the output state of the circuit 9. Note that the output of the NOR circuit 15 is 0". On the other hand, both the third gate circuit 7 and the analog switch SW3 are turned on, and the mass/medium wheel of the arithmetic amplifier 3 becomes 16. Therefore, Each logical value from the 5th pick l-d to the 12th pick d is the 3rd pick.
The signal is input to the converter 1 through the gate circuit 7 and converted into an analog signal. This analog signal is then outputted via the switch 2 and the operational amplifier 3. In this case, since the amplification rate of the operational amplifier 3 is 16 due to the analog switch SW3 being turned on, the amplification rate is 1024 in the L range.
mV~4080mV, 102.4 mV~ in H range
An analog output in the range of 408.0 mV is obtained. Furthermore, if a logical value of 1 is entered in either or both of the 13th bit 'd12 and the 14th bit dl, the OR circuit 11
The result will be °"1". As a result, switch element 1
2.13 is turned off, so the third circuit 7 and the analog switch SW3 are both turned off, and the fourth gate circuit 8 and analog switch SW4 are turned on instead. The width ratio is 64. Then, each logical value from the seventh hit d6 to the fourteenth hit I' dl:l is input to the converter 1 via the fourth gate circuit 8 and converted into an analog signal. This analog signal appears at output terminal 4 via switch 2 and operational amplifier 3 with amplification factor 64. In this case, in the L range state with switch -2 set to fixed contact a side, the minimum voltage appearing at output terminal 4 is 64 mV x 64 = 4096 mV (d +
Each logical value of s to d6 suddenly becomes [0100OOOOJ], which exceeds the L range, so switch 2 is set to H.
It will be used by switching to the fixed contact on the range side. This results in an output voltage ranging from 409.6 mV to 998.4 mV. Incidentally, at 998.4 mV, each logical value of 16 humans is [oo+zooJ.

The results of the above processing are shown in the table below.

(The following is a blank space) As is clear from the description of the embodiments described above, according to the present invention, a digital signal having an m-hit configuration output from a digital device is processed by a predetermined number of hits starting from the least significant bit of the digital signal, and The most significant bit whose logic value is "l" is detected among the upper m-n bits of the digital signal excluding the □ bit of the lowest group, and the position of this most significant bit is also Then, one of the above-mentioned Hira I, Kuru, and '1b is 1) of n people.
/A.

-f' By converting the signal into an analog signal using a converter and amplifying the analog signal by a predetermined factor, a digital signal composed of m hits (for example, 14 hits) can be converted into a digital signal with a larger number of bits. D with less n bits (e.g. 8 bits)
It can be converted into an analog signal using a /A converter, which is extremely advantageous in terms of cost. In that case, the resolution in the above example is 0.4 in relation to the amplification rate (Kane).
% to 06chi (G), and the error included in the indicated value when switching the gain is 16chi, but this value is within the error range required for normal g) regulators and is practically in most cases No problem.0 In the above embodiment, 14-hit digital signals are converted into 8
When dividing the croup into croup by hit, even 2 croup are divided into each croup, but the present invention is not limited to this. In other words, depending on the number of output hits output from the digital device, it may be difficult to shift the output by 3 hits, and the amplification rate in that case is (2:l).
n == 8n1 However, ng is an integer from 0 to (the number of croup - 1), and the amplification rate multiplied by it should be increased as it becomes a higher croup.

[Brief explanation of the drawing]

The figure is a block diagram of a digital-to-analog conversion output device according to the present invention. In the figure, l is a D/A converter, 2 is a range selector switch, and 3 is a D/A converter.
is an arithmetic amplifier circuit, 5 to 8 are gate circuits, and 9 to 11 are OI
(Circuit, 12 to 11 are switch elements, 15 is a NOR circuit. Patent applicant: Hioki Electric Co., Ltd.

Claims (1)

[Claims] A digital-to-analog conversion output device that converts a digital signal of m-hit configuration output from a decile device into an analog signal using an n-bit D/A converter having a smaller number of bits, and outputs the analog signal, A digital signal having a bit configuration is shifted by a predetermined number of bits from the least significant bit and divided into groups redundantly every n bits, and a plurality of gate circuits assigned to each of the bit groups and the least significant bit of the digital signal A position detecting means for detecting the most significant bit whose logical value is IIJ among the upper mn bits excluding n bits of the group; and a signal from the hit position detecting means to detect the bit through the circuit bit group selection means for inputting any one of the selected groups into the converter; and amplifying the analog output of the D/A converter by a magnification selected by a control signal from the bit group selection means. 1. A digital-to-analog conversion output device, characterized in that it is equipped with amplifying means.