JPS60105322A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To minimize the harmonic distortion factor by giving a potential of a half of the sum of two reference potentials Vcc and Vss to a reference bias terminal and a midpoint bias terminal respectively so as to attain an ideal bias state. CONSTITUTION:A bias circuit 20 providing a potential of (Vcc+Vss)/2 to the reference bias terminal 14 and the midpoint bias terminal 16 respectively as bias potentials VT and VM is provided. An analog output VOUT changes around the (Vcc+Vss)/2 so as to prevent a shift of VLSB/2. Thus, the voltage biasing the LSB side termination part of a resistor ladder network LA is nearly (Vcc+ Vss)/2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter having an R-2R type resistance ladder network, which minimizes harmonic distortion and improves temperature characteristics by specifying bias conditions. be.

Conventionally, this type of digital-to-analog converter is
A circuit configuration as shown in FIG. 1 is known.

The circuit shown in Figure 1 is for obtaining a voltage output by converting a 10-bit digital input from analog to analog. Signal D
It includes an R-2R type resistor ladder network LA that performs a near DA conversion operation as an O to D9 Y input.

The analog switches SO to S9 change the relatively low reference potential VS8 of the first reference potential terminal 10 according to the digital input.
(=“L”) or the relatively high reference potential vcC (=“H”) of the second reference potential terminal 12 is selected, and the resistance ladder network L
It is designed to be supplied to A.

The terminal end on the lowest pin (LSB) side of the resistor ladder network LA is connected to the reference potential VT via the resistor 2RY.
A reference terminal 14 is connected to the reference terminal 14 for supplying V. Also, the topmost pin of the resistance ladder network LA) (MSB
) side, an analog output terminal 18 is connected, and this terminal 18 is connected to the midpoint terminal 16 via a resistor RM'&. A midpoint bias potential VM for determining the center of the swing of the L1 analog output VOUT is applied to this terminal 16.

Fig. 2 shows the input/output characteristics of the circuit shown in Fig. 1, where the horizontal axis shows the ladder resistance input (Do-DO'') supplied from the analog switch 5ob-8s to the resistance ladder network LA, and the vertical axis shows the input/output characteristics of the circuit shown in Fig. 1. The axis shows analog output VOUT, ladder resistance input (or digital input) as shown in Figure 2.
is linearly converted to DA. Note that at point A, if all bits of DQ-DO are low, at point 8, only the DO (MSB) is low.
If all other bits are 'H', the 0 point is the point between B and D, and at the D point, only DO is 'H' and all other bits are '1'.
In the case of , point E is shown when all bits of DO-DO are H''.

In the circuit as described above, if it is desired to swing the analog output around an appropriate voltage value, the midpoint bias potential VMY may be determined as appropriate. For example, if , the center of the analog output swing is approximately (Vcc
+Vss)/2 yal- Swings centered.

However, strictly speaking, the center of the swing of the analog output is not (VCC+V8B)/2.

The reason for this is that in the conventional configuration, as shown in FIG. 3, the reference bias terminal 14i is connected to the first reference potential terminal 10, so the analog output swings around . . That is, as shown in Fig. 4, the center of the deflection is (vcc +VS8) /2, so DV=VL
It will be shifted by 8B/2. In addition, VL8B is Do
This is an analog output voltage when only (LSB) is 6L" and all other bits are H".

If a sine wave output is generated as an analog output by DA conversion in a state where the center of the deflection is shifted in this way, the harmonic distortion rate will be large as shown in FIG. 5, and the AC accuracy will be poor.

In this case, in order to minimize the harmonic distortion rate, the following should be used. Therefore, conventionally, as shown in Fig. 3, a voltage divider circuit consisting of resistors r, rQ, and r' connected in series was provided between VCC and VSS, and the voltage formed by resistor rQ was taken out and passed through the buffer BFY to the terminal. 16 as a midpoint bias potential VM.

However, with such a configuration, it is not only troublesome because it is necessary to adjust the resistor ro'1 externally, but also because the temperature characteristics of the resistors that make up the voltage divider circuit do not match, the temperature of the digital-to-analog converter may change. There was a drawback that the characteristics deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a novel digital-to-analog converter that eliminates these drawbacks and minimizes harmonic distortion.

The digital-to-analog converter according to the present invention is characterized in that a potential that is 1/2 of the sum of two reference potentials VCC and VSS is applied to the reference bias terminal and the midpoint bias terminal, respectively. , the embodiments shown in the accompanying drawings will be described.

FIG. 6 shows a circuit configuration Z of a digital-to-analog converter according to an embodiment of the present invention, and the same parts as in FIG.

The circuit shown in FIG. 6 has bias potentials VT and VM applied to the reference bias terminal 14 and midpoint bias terminal 16, respectively.
As a result, a bias circuit 20 is provided which provides a potential of (Vcc+Vss)/2. In this way,
Analog output vOUT is (Vcc+Vss)/2 yx
This allows the vibration to be centered, thereby eliminating the VLSB/2 deviation t mentioned above.

Also, by doing this, the LSB of the resistance ladder network LA
The voltage that biases the side termination is approximately (Vcc +Vss
)/2 for the following reason.

In other words, the voltage at the center of the analog output swing is as follows.The difference in (Vcc Vss)/2 at the termination section creates a difference of VLSB/2, so for example, if the voltage at the termination section is the difference in VL8B/8, This is within the permissible range. The terminal voltage error (vcc-Vss)/8 at this time is, for example, 1.
25 [v], CVCCfVSS )/2=5
(V), it is possible to deviate by about 1.2 [V].

FIG. 7, FIG. 8, and FIG. 9 all show specific examples of adding a bias circuit.

In the circuit shown in Fig. 7, the circuit in which the terminal 14 is connected is connected in series with two resistors 2R between VCC and VSB to form a voltage divider circuit, and from the interconnection point of the two resistors (VC
Take out the potential C+V8S)/2 and apply it to the terminal 14,
The resistor (connected to terminal 14 on the resistor ladder network side) is R instead of k2R, and such a circuit configuration has terminal 14Y connected to resistor 2R as shown in Figure 6.
(VCC+VBB)/2 te/' (Equivalent to a circuit that biases 7 terminals. Also, a circuit that biases terminal 16 is
Two resistors RIY are connected in series between VCC and VSS to form a voltage divider circuit, and a potential of (Vcc + Vss)/2 taken out from the interconnection point of the two resistors is applied to the terminal 16 via the buffer 22. This is what I did.

The circuit shown in FIG. 8 is constructed by paying attention to the fact that the potential at the output end of amplifier 4 is (Vcc +Vss)/2 in the circuit shown in FIG.

In the circuit of FIG. 9, a potential (Vcc + Vss)/2 taken out from a voltage dividing circuit including two resistors R1 is applied to a terminal 14 through separate buffers 22A and 22B.
and 16.

FIG. 10 shows a digital computer according to another embodiment of the invention.
It shows an analog converter.

R-2R type resistor ladder network L from digital input terminal IN
A has an input buffer BFo- provided for each bit.
Digital input is provided via BF9'4. A reference bias terminal 14 is connected to the LSB side terminal portion of the resistor ladder network LA via a resistor 2RY. Further, an R-2R wave attenuation path LAQ consisting of RO and 2RQ resistors is connected between the MSB side of the resistance ladder network LA and the midpoint bias terminal 16.

The reference bias terminal 14 and the midpoint bias terminal 16 include
As described above with reference to FIGS. 6 to 9, the bias circuits provide the 5 ia smi levels VT and 'VM, respectively.

From the plurality of output terminals of the attenuation circuit LAQ, (V(H+VM
)/2=V01-1, multiple analog voltages with exponentially different attenuation degrees are generated in parallel, and these analog voltages are connected to multiple output terminals of the attenuation circuit LAo. In response to the ON operation of any of the analog switches ASO-ASi connected between the analog output terminal 18 and the analog output terminal 18, the signal is selectively output as an analog output votr'r.

FIG. 11 shows the resistance value distribution when a large number of thin film resistor intervals of the same size are formed on a semiconductor wafer by sputtering. The resistance value of the thin film resistor is the 11th
As shown in the figure, it tends to increase as it falls from the center of the wafer. Therefore, it is preferable to adopt an arrangement in which the values of the resistors connected to the bias circuits VCC and VSB are made as equal as possible as shown in FIGS. 7 to 9.

FIGS. 12 and 13 show thin film resistor arrangements effective for making the resistance values equal on the VCC side and the VSS side.

In the example shown in Fig. 12, four thin film resistors of the same size are arranged side by side at the same spacing in the direction away from the center of the wafer, and between the two central thin film resistors R8I and R82Y VSS and the midpoint terminal PM. They are connected in series, and are connected in series between the two thin film resistors RCI and RC2'k Vcc on both sides of R8I and R82 and the midpoint terminal PM.

FIG. 13 shows 6
Two thin film resistors are arranged side by side at the same interval, and the four thin film resistors in the center are resistors R8I and R82 for V8s and V
Divide into left and right pairs with CC resistors RC2 and RC3, and use the outer thin film resistor of the left pair of resistors as VCC resistor RC.
□, thin film resistor 7 on the outside of the right set of resistors: vss
IRsa, resistors RCI to RC3Y are connected in series between VCC and the midpoint terminal PM, and resistors R8I to R83'! are connected between VSB and the midpoint terminal PM. 'They are connected in series.

In addition, in FIGS. 12 and 13, RDI and RD
2 is an unused dummy thin film resistor that is placed adjacent to the outermost thin film resistor at the same spacing as the thin film resistor interval, and by placing these dummy thin film resistors, the etching accuracy of the outermost thin film resistor is improved. Therefore, the difference between the total resistance on the VCC side and the total resistance on the VSS side can be further reduced.

As described above, according to the present invention, two reference potentials VCC are provided at the reference bias terminal and the midpoint bias terminal, respectively.
Since a potential of 1/2 of the sum of and vss is applied, the deviation of VL8B/2 that existed conventionally can be eliminated. Therefore, it is possible to minimize harmonic distortion and overtones while maintaining an ideal bias state. In addition, since there is no need to provide an external resistor for bias adjustment, it not only saves the effort of bias adjustment, but also makes it possible to construct a voltage divider circuit with two resistors with the same temperature characteristics and the same resistance value. ), which also has the effect of improving the temperature characteristics of the digital-to-analog converter.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional digital-to-analog converter, Figure 2 is an input/output characteristic diagram of the circuit in Figure 1, and Figure 3 is a circuit diagram showing a modification of the circuit in Figure 1. , FIG. 4 is an input/output characteristic diagram of the circuit of FIG. 3, and FIG. 5 is a graph showing the relationship between the midpoint bias potential and harmonic distortion rate in the circuit of FIG. 3.
FIG. 6 is a circuit diagram showing a digital-cito analog converter according to an embodiment of the present invention; FIGS. 7, 8, and 9 are circuit diagrams showing different configuration examples of the bias circuit; The figure shows a digital computer according to another embodiment of the invention.
A circuit diagram showing an analog converter, Fig. 11 is a graph showing the resistance value distribution when a large number of thin film resistors of the same size are formed on a wafer, and Figs. 12 and 13 are diagrams configuring a voltage dividing circuit. FIG. 4 is a plan view showing different examples of thin film resistor arrangement for the purpose of the present invention. 10... First reference potential terminal, 12... Second reference potential terminal, 14... Reference bias terminal, 16... Midpoint bias terminal, 18... Analog output terminal, addition...
・Bias circuit, So~S9...analog switch,
LA...R-2R type resistance ladder network. Applicant: Nippon Gakki Mfg. Co., Ltd. Agent Patent Attorney: Toshiaki Izawa Rutter / Side entry category V゛Cle input Fig. 5 Fig. 7 Fig. 11') 7 ゛ f vector Fig. 12 Fig. 13 VCCVS8

Claims (1)

[Claims] (a) Relatively low first reference potential! a second reference potential source that provides a relatively high second reference potential; (C) a plurality of input terminals each corresponding to a plurality of bits of digital input; (d) an R-2R type resistor ladder network having a reference bias terminal at the bit side terminal part via a terminating resistor and converting signals from the plurality of input terminals into linear DA; A plurality of correspondingly provided analog switches,
Selecting the first or second reference potential in response to each of the plurality of bits of the digital input signal, and supplying each selected reference potential to the corresponding input terminal of the R-2R type resistor ladder network. and (e) an output circuit for extracting an analog output from the R-2R resistor ladder network, having a midpoint bias terminal;
In the digital-to-analog converter, the center of the swing of the analog output is determined according to the potential of the midpoint bias terminal, and the reference bias terminal and the midpoint bias terminal each include: A digital-to-analog converter comprising a bias circuit that provides a potential equal to 1/2 of the sum of the first and second reference potentials.