JPS6110278A - Mos type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To speed up by reducing the substrate capacitance, and to stabilize the action by a method wherein miniaturization is attained by unnecessitating mask margins by self-alignment. CONSTITUTION:Polycrystalline Si wirings 115 and 116 make contacts with each of source region made of a shallow junction 107 and a deep N<+> diffused layer 111 and the drain region made of a shallow N<+> diffused layer 108 and a deep junction 112 in self-alignment with a gate electrode 104. This unnecessitates margins for positioning and then enables the improvement in integration by markedly reducing the areas of the source and drain regions. Further, the flow of current becomes uniform because of uniform connection of the polycrystalline Si wirings 115 and 116 to the deep N<+> diffused layers 111 and 112 in the width direction of the gate electrode 104, and the variability in stability and characteristics of the element is small. Moreover, the capacitance between the source and drain regions and the Si substrate 101 reduces, and the operating speed of the element markedly improves.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a MOS type semiconductor device and a method for manufacturing the same.
In particular, the present invention relates to a MOS type semiconductor device in which wiring connections to a source and drain are formed in a self-aligned manner with respect to a gate region, and a method for manufacturing the same.

(Prior Art) The demand for higher integration of integrated circuit devices, especially MOS type integrated circuit devices, is increasing year by year, and miniaturization of elements has therefore become an essential condition.

A MOS type device consisting of a gate region, source and drain regions is designed to reduce the overall area of the device by reducing the length and width of the gate and the area of the source and drain regions. However, in order to transmit electric signals to the outside, it is necessary to provide contact holes for connecting metal wiring in the source/drain regions, which are made up of diffusion layers to the substrate. At this time, if the contact hole is not completely included in the diffusion layer when viewed from above, the metal wiring and the substrate will be electrically short-circuited, the potential of the metal wiring will be the same as that of the substrate, and no signal will be transmitted. I end up. In order to avoid this problem, it is necessary to provide a certain amount of space between the contact hole and the edge of the source/drain region, especially between the gate region and the contact hole. However, the size of the contact hole is limited by the size of the contact hole, and the size cannot be reduced below a certain value, which poses a major problem in that the degree of integration cannot be improved.

(Objective of the Invention) The object of the present invention is to eliminate the above drawbacks, achieve miniaturization by eliminating the need for a mask margin through self-alignment, reduce capacitance between substrates, increase speed, and stabilize operation. An object of the present invention is to provide a MOS type semiconductor device and a method for manufacturing the same.

(Structure of the Invention) A MOS type semiconductor device according to a first aspect of the present invention has a shallow junction first source/drain region in contact with a gate region consisting of at least a gate insulating film and a gate electrode, and the shallow junction The first source/do faces of the gate region are covered with wiring formed in a self-aligned manner with respect to the gate region.

The method for manufacturing a MOS type semiconductor device according to the second aspect of the present invention further includes a step of etching a gate electrode and a gate insulating film using a photoresist as a mask to form a pattern, and a step of forming a pattern between the photoresist, the gate electrode, and the gate insulating film. A step of introducing an impurity of a conductivity type opposite to that of the substrate using the film as a mask to form a shallow junction of LCX, and a step of forming an insulating film only on the side surface of the gate electrode while leaving the photoresist.
using the photoresist, the gate electrode, the gate insulating film, and the insulating film on the side surface of the gate electrode as a mask to introduce an impurity having a conductivity type opposite to that of the substrate to contact the first junction and form an R junction; , a step of forming a conductive film serving as wiring to the source and drain on the entire upper surface including the photoresist, and a step of simultaneously removing the conductive film on the gate electrode by removing the photoresist. It is composed of various parts.

Further, a method for manufacturing a MOS type semiconductor device according to a third aspect of the present invention includes a step of etching a gate electrode and a gate insulating film pattern on a semiconductor substrate of one conductivity type using a photoresist as a mask; A step of introducing an impurity of a conductivity type opposite to that of the substrate using the gate electrode and gate insulating film as a mask to form a first shallow junction, and a step of forming an insulating film only on the side surface of the gate electrode while leaving the photoresist. a step of forming a conductive film serving as wiring to the source/drain on the entire upper surface including the photoresist; a step of removing a thin conductive film on the insulating film on the side surface of the gate electrode; and a step of removing the photoresist. Accordingly, the method includes a step of simultaneously removing the conductive film on the gate electrode, and a step of implanting ions of impurities of a conductivity type opposite to that of the substrate into the substrate through the conductive film constituting the wiring to form a deep junction. Ru.

(Function) In the MOS semiconductor device of the present invention, the deep junction layer simultaneously plays the role of a contact hole, and the wiring is formed in self-alignment with the gate region. Margins at the edges of the area are no longer required, and M
A significant effect is obtained in that the area of the OS element is significantly reduced. For this reason, when integrated, the design rule is
μm1-J.

If it becomes VLSIK, it will have the great advantage of dramatically increasing the degree of integration. Furthermore, since the contact portion is formed uniformly along the gate edge, there is no variation in current along the gate width, which has the advantage of providing a highly stable MOS type device. become. In addition, the source/drain region can be made smaller, and the capacitance between the source/drain and the substrate can be reduced.
It is advantageous to have the advantage of increasing speed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 (al to (fl) are sectional views shown in the order of steps to explain the first embodiment of the present invention and its manufacturing method.

First, as shown in FIG. 1(a), a thick oxide film 102a is selectively formed in the field portion of the P-type silicon substrate 101.
, 102b, a region other than the field region,
That is, a silicon oxide film for the gate, a polycrystalline silicon film doped with impurities to serve as the gate electrode, and a silicon oxide film for maintaining insulation on the upper part of the gate electrode are sequentially formed in the active region, and the gate is removed using a photoresist as a mask. Silicon oxide film on top of the electrode, polycrystalline silicon film that will become the gate electrode.

A gate oxide film 103 that is patterned by sequentially etching the silicon oxide film for the gate. Gate electrode 104.
silicon oxide film 105, photoresist) 10
Using this multilayer structure as a mask, ions of, for example, arsenic are implanted to form N+ diffusion layers 107 and 108 with a shallow Q and a thickness of about 1 μm.

Next, as shown in FIG. 1 (fb), a silicon oxide film 109 is grown over the entire surface by a film growth method such as photo-CVD or plasma CVD at a low temperature and with good step coverage.

Next, as shown in FIG. 1, by etching the entire surface of the silicon oxide film 109 using reactive ion etching, a sidewall silicon oxide film 110a, 1 lob is formed only on the end portion of the gate electrode 104.
form. Next, using the sidewall silicon oxide films 110a, 110b and the multilayer structure as a mask, arsenic ions are implanted to form deep N 2 diffusion layers 111, 112.

Next, as shown in FIG. 1 d), a polycrystalline silicon film 113 doped with impurities is grown over the entire surface by a method of forming a film with poor step coverage, such as sputtering or ion beam deposition. .

Next, as shown in FIG. 1, the entire surface of the polycrystalline silicon 112 is slightly etched to remove the thin polycrystalline silicon 114a, 114b grown on the sidewall silicon oxide films tioa, 110b.

Next, as shown in FIG. 1ff), a photoresist 10
6 is removed, the polycrystalline silicon film 113 on the photoresist is removed by lift-off, and the remaining polycrystalline silicon film 113 is etched into a required pattern to form polycrystalline silicon wirings 115 and 116.

As described above, a MOS type semiconductor device ioo according to the first embodiment of the present invention is obtained.

A source region consisting of a diffusion layer 111 and a shallow N+ diffusion layer 1
08 and deep junction 112, each of the drain regions consists of
Since contact is made with the gate electrode 104 in a self-aligned manner, there is no need to provide a margin for alignment between the contact hole and the gate electrode 104, and the area of the source region and drain region can be reduced. It becomes possible to significantly reduce the size and improve the degree of integration. 1 more
Since the polycrystalline silicon interconnections 115 and 116 are connected to the deep N+ diffusion layers 111 and 112 uniformly in the width direction of the gate electrode 104, the current flow is uniform, and the stability of the device and variations in characteristics are reduced. It also has the advantage of being small. Furthermore,
Since the area of the source region and the drain region is reduced, the capacitance between the source region, the drain region, and the silicon substrate 101 is reduced, and the operating speed of the device is also greatly improved.

FIG. 2 (tag, fb) are cross-sectional views shown in the order of steps for explaining the second embodiment of the present invention. The second embodiment is manufactured using the same method as the first embodiment except for forming a deep N+ diffusion layer, and as shown in FIG. 2, a P-type silicon substrate 201. Field silicon oxide films 202a, 202b, gate silicon oxide film 203
, gate electrode 204, insulating silicon oxide film 20
5. Sidewall silicon oxide film 210a, 210b
, shallow junctions 207 and 208, and wiring 213 are formed.

Next, as shown in FIG.
Arsenic is ion-implanted into 1 to form deep junctions 211 and 212.

In this second embodiment 200, when ion-implanted arsenic is activated, K, wiring and shallow N+ diffusion layer 207,
In order for the arsenic implanted into the P-type silicon substrate 201 to diffuse into the P-type silicon substrate 201, the P-type silicon substrate 201 and the wiring 21
There is no direct contact between P-type silicon substrate 201 and the wiring 213, and an N+ layer is always formed under the wiring 213, which has the advantage of reducing leakage between the P-type silicon substrate 201 and the wiring 213.Furthermore, the wiring 213 has a high melting point. In the case of metal, it also has the great advantage that ohmic contact between the deep junctions 211, 212 and the wiring 2130 can be easily made due to the mixing effect during ion implantation.

In the detailed explanation of the present invention, the source/drain wiring was formed in a self-aligned manner with respect to the gate region by using a photoresist or by the 7-off method. In the case of silicon, it goes without saying that if a material such as Ag that can be etched with an etching solution or gas that does not attack the wiring material is used as the lift-off material, the sidewall silicon oxide film can be grown at a much higher temperature. .

(Effects of the Invention) As explained above, according to the present invention, the source/drain contacts are made in a self-aligned manner with respect to the gate electrode, so no mask margin is required, and the size is smaller than K. As a result, a MOS type semiconductor device with a small capacitance between substrates, high speed, and stable operation can be obtained.

[Brief explanation of drawings]

Fig. 1 tal to ffl are sectional views shown in the order of steps to explain the first embodiment of the present invention, Fig. 2 tag, (b
FIG. 1 is a cross-sectional view shown in order of steps for explaining a second embodiment of the present invention. 101, 201-...=P-type silicon substrate, 102
a. 102b, 202a, 202b-74-, oxidized film, 1
03, 203 ... = ... gate oxide film, 104, 20
4...Gate electrode, 105, 205...
・Silicon oxide film, 106--7s) L/cyst, 1
07,108,207°208...Shallow N+ diffusion layer, 109...Silicon oxide film, 110a,
110b, 210a, 210b - Length side wall silicon oxide film, 111, 112° 211.212.
...Deep N diffusion layer, l l 3.213...
・・・Polycrystalline silicon film, 114a, 114b...°・
・Thin polycrystalline silicon L Li2,116 formed on the sidewall...Polycrystalline silicon wiring, 100°200...MOS of the embodiment of the present invention
type semiconductor device. 1 figure ¥1 top 2#b 2ef Fujita

Claims (5)

[Claims] (1) A first source/drain region with a shallow junction is in contact with a gate region consisting of at least a gate insulating film and a gate electrode, and a second source/drain region with a deep junction is in contact with the first source/drain region of the shallow junction. It has source and drain regions of
A MOS type semiconductor device characterized in that the entire surface of the second source/drain region is covered with wiring formed in self-alignment with the gate region. (2) forming a gate electrode and a gate insulating film pattern on a semiconductor substrate of one conductivity type by etching using a photoresist as a mask; a step of introducing an impurity to form a first shallow junction; a step of forming an insulating film only on the side surface of the gate electrode while leaving the photoresist; and the photoresist/gate electrode;
A step of introducing an impurity of a conductivity type opposite to that of the substrate using the gate insulating film and the insulating film on the side surface of the gate electrode as a mask to form a junction deeper than the first junction by contacting the first junction, and the entire upper surface including the photoresist. A MOS type semiconductor device comprising the steps of: forming a conductive film to serve as wiring to the source and drain; and simultaneously removing the conductive film on the gate electrode by removing the photoresist. Production method. (3) forming a gate electrode and a gate insulating film pattern on a semiconductor substrate of one conductivity type by etching using a photoresist as a mask; A step of introducing impurities to form a first shallow junction, a step of forming an insulating film only on the side surface of the gate electrode while leaving the photoresist, and a step of forming an insulating film on the entire upper surface including the photoresist to the source and drain. a step of forming a conductor film to serve as a wiring; a step of removing a thin conductor film on an insulating film on a side surface of the gate electrode; and a step of simultaneously removing the conductor film on the gate electrode by removing the photoresist. 1. A method for manufacturing a MOS semiconductor device, comprising the step of ion-implanting impurities of a conductivity type opposite to that of the substrate into the substrate through a conductive film constituting wiring to form a deep junction. (4) A method for manufacturing a MOS semiconductor device according to claim (1) or (2), characterized in that an insulating film is interposed between the photoresist and the gate electrode. (5) As the insulating film on the side surface of the gate electrode, a silicon oxide film or a silicon nitride film grown by a photo-CVD method is used.
3) A method for manufacturing a MOS type semiconductor device as described in section 3).