JPS61100955A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61100955A JPS61100955A JP22171284A JP22171284A JPS61100955A JP S61100955 A JPS61100955 A JP S61100955A JP 22171284 A JP22171284 A JP 22171284A JP 22171284 A JP22171284 A JP 22171284A JP S61100955 A JPS61100955 A JP S61100955A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- grounding
- conductor
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体装置に関し、特に半絶縁性半導体基板上
に形成さn1出力波形の低虫化が容易な超高速論理回路
装置に関する0
(従来の技術Pよびその問題点)
ひ化ガリウム基板上に、例えは従来のMESFET構造
を有する能動素子を形成したモノリシ、り集積回路(I
C)La、、ひ化ガリウムの高電子移動度による高速性
t−Mするため、特に超高速ディジタルICにおいて注
目さiている0例えは1通信装置の局部発根器の安定化
に使用される超高速分局器等に訃いては、GaAsモノ
リシ、りICの使用によ多数GHzでの動作が可能とな
シ、マイクロ波通信分野において極めて重要な役割と期
待されている。ところで、従来のG a A s超萬速
論理ICは出力信号波形にクロック信号の訪尋雑音に起
因した出力波形歪が存在し、%にマイクロ波通信用超扁
速分周器においては実用上貞犬な問題が生じている。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device, and more particularly to an ultrahigh-speed logic circuit device formed on a semi-insulating semiconductor substrate and capable of easily reducing the n1 output waveform. technology P and its problems) Monolithic integrated circuits (I
C) La, is attracting attention especially in ultra-high-speed digital ICs because of its high speed t-M due to the high electron mobility of gallium arsenide. The use of GaAs monolithic integrated circuits (ICs) enables operation at multiple GHz, and is expected to play an extremely important role in the field of microwave communications. By the way, in the conventional GaAs ultra-high-speed logic IC, there is output waveform distortion in the output signal waveform due to interfering noise of the clock signal, and it is practically impossible to use an ultra-flat frequency divider for microwave communication in %. I have a dog problem.
第2図は、従来の1/2分周器集積回路装置の平面図で
ある。弗1図において、1はクロック人カパッド、破線
内領域2はひ化ガリウム基板3上に通常の方法にて形成
さnた分周器回路部分、4は出力パッド、5は分周器回
路部分2と出力パッド4とを接続する出力信号接続線で
るる。FIG. 2 is a plan view of a conventional 1/2 frequency divider integrated circuit device. In Figure 1, 1 is a clock pad, area 2 within the broken line is a frequency divider circuit formed on a gallium arsenide substrate 3 by a conventional method, 4 is an output pad, and 5 is a frequency divider circuit. An output signal connection line connects the output pad 4 and the output pad 4.
このような構成の集&(ロ)路装置のクロック入力パッ
ド1に超高周波のクロック信号が印加された場せ、クロ
ック16号区人カバ、ド1及びその給電線忙放射源とし
て空気中及び半絶縁性ひ化ガリウム基板内部に雑音信号
を放射する0この雑音は出力信号接続#5及び出力パッ
ド4において誘導雑音として現れる。本発明肴の実験に
よnは、上記現象は、通常IC電源電圧値を零としても
出力波形にクロ、り信号と四−の周波数tVする雑音と
して実際に確認されている。If an ultra-high frequency clock signal is applied to the clock input pad 1 of the collector and (b) circuit device with such a configuration, the clock 16, the clock 16, and its feeder line will be used as radiation sources in the air and This noise radiates a noise signal inside the semi-insulating gallium arsenide substrate and appears as induced noise at output signal connection #5 and output pad 4. According to experiments conducted using the present invention, the above-mentioned phenomenon has actually been confirmed as noise having a frequency of tV equal to or equal to the signal in the output waveform even when the IC power supply voltage value is zero.
このように上記従来の1/2分周器ICにおいてに、出
力波形に歪を生ずる0、第3図は上記出力波形の歪を説
明するための図で、第2図の1/2分周器の出力波形を
ある##足のクロ、り周波数においてモニタした一例で
める。同図において、11は出力の172分周波形、1
2は前述し九クロ。In this way, in the conventional 1/2 frequency divider IC, distortion occurs in the output waveform. Here is an example of monitoring the output waveform of the device at a certain frequency. In the same figure, 11 is the output frequency divided by 172 waveform, 1
2 is nine black as mentioned above.
りの誘導雑音でめる。従って結果として得られる出力波
形は両者の和として13で示された歪の多い波形となる
0更に、クロック周波数が変化するとクロック誘導雑音
電圧振幅及び1/2分周波形11と誘導雑音成分12と
の位相関係の両省が変化するため、実際の出力波形13
は、クロック周波数により変化するという欠点が存在す
る。このため従来は上記出力波形モニタ図するため分周
器IC後部にクロ、り雑音除去用のフィルタ等を接続す
る必要がめシ、実用上極めて不便でろう九〇なお、上述
の説明では1/2分周器ICを一例として説明しkが、
上記欠点は他のび化ガリウムを用いた超尚速論理菜槓回
路にも存在していることは言うlでもない。It is caused by the induced noise. Therefore, the resulting output waveform becomes a highly distorted waveform shown by 13 as the sum of both. Furthermore, when the clock frequency changes, the clock induced noise voltage amplitude, the 1/2 frequency divided waveform 11, and the induced noise component 12 change. The actual output waveform 13 changes because both phases of the relationship change.
has the disadvantage that it changes depending on the clock frequency. For this reason, in the past, it was necessary to connect a filter for eliminating noise at the rear of the frequency divider IC in order to monitor the output waveform, which was extremely inconvenient in practice. Taking a frequency divider IC as an example, k is
Needless to say, the above drawbacks also exist in other ultrafast logic circuits using expanded gallium oxide.
本発明の目的に、従来の問題点を改善し、フィルタ等を
用いることなく容易に出力波形歪を低減し得る集積回路
をMする半導体装tを提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device t including an integrated circuit which can improve the conventional problems and easily reduce output waveform distortion without using a filter or the like.
(問題点r′j!%決するだめの手段)本発明は半絶縁
性半導体基板上に形成された集積回路と、この集積回路
への入出力端子用ポンディングパッド及び入出力信号接
続*tWする半導体装置において、これらの周曲に接地
用得体を配置したことを特徴とする。(Means to resolve the problem r'j!%) The present invention provides an integrated circuit formed on a semi-insulating semiconductor substrate, and bonding pads for input/output terminals and input/output signal connections to this integrated circuit. The semiconductor device is characterized in that grounding bodies are arranged on these circumferential curves.
(実施例) 以下、本発明について図面を参照して説明する。(Example) Hereinafter, the present invention will be explained with reference to the drawings.
第1図は、本発明の半導体装置の一実施例の平面図でる
る0同図において、lは入力パッド、2はひ化ガリウム
基&3上に通常の方法にて形成された分周器回路部分、
4は出力パッド、5は出力信号接続機、6は入出カバ、
ド及び入出力信号接続線に近接して配置された接地導体
パターンでるる〇
本発明の構造の半導体装置に依れは、従来、ひ化ガリウ
ム基板3の一生表面上に形成された入出力端子パッドと
基板3の層面に形成ちれる接地導体との対により形成て
れていた放射源と比べ、入出力端子パッドと接地導体と
の距離を格段に麹少し得る。従って、従来、チップサイ
ズに比べ比較的広い範囲に放射賂れていたクロック信号
の防導雑音電界は、クロ、り入力端子パッド近傍に局在
化もれ、また蚕く同様に出力端子パッドと接地導体との
距離も縮少式れているため、クロック信号の妨碍雑音2
に受けにくく成る◇したがって従来技術に比して、出力
i&L極に2けるクロック信号の誘導雑音を容易に低減
し得、従来、問題となっていた出力信号の波形1!!を
容易に改吾し得る〇なお、上記実施例ではGaAs基板
上に分周器回路を設けた場曾について述べたが、他の半
絶縁性半纏体基版上に集積回路を形成したものについて
も通用可能なことは明らかでるる。FIG. 1 is a plan view of an embodiment of the semiconductor device of the present invention. In the same figure, l is an input pad, 2 is a frequency divider circuit formed on a gallium arsenide base & 3 by a conventional method. part,
4 is an output pad, 5 is an output signal connector, 6 is an input/output cover,
In the semiconductor device having the structure of the present invention, the input/output terminals conventionally formed on the surface of the gallium arsenide substrate 3 are grounded conductor patterns arranged close to the terminals and the input/output signal connection lines. Compared to a radiation source formed by a pair of a pad and a ground conductor formed on the layer surface of the substrate 3, the distance between the input/output terminal pad and the ground conductor can be significantly reduced. Therefore, the conductive noise electric field of the clock signal, which conventionally was radiated over a relatively wide range compared to the chip size, is now localized near the input terminal pad, and is also radiated to the output terminal pad. Since the distance to the ground conductor is also reduced, interference noise of the clock signal2
◇ Therefore, compared to the conventional technology, the induced noise of the clock signal at the output I & L poles can be easily reduced, and the waveform of the output signal, which has been a problem in the past, can be reduced. ! can be easily modified. In the above embodiment, the frequency divider circuit is provided on a GaAs substrate, but the integrated circuit may be formed on other semi-insulating semi-integrated substrates. It is clear that it is also applicable.
(発明の効果)
以上の様に、本発明によれは、入力信号の誘導雑音に起
因する出力波形の歪を容易に除去でき、従って、外部フ
ィルタを使用する必要もない◇又、入力信号絢波数によ
る出力波形の変化等の従来技術の欠点全容易に改善し侮
る。(Effects of the Invention) As described above, according to the present invention, the distortion of the output waveform caused by the induced noise of the input signal can be easily removed, and therefore there is no need to use an external filter. All of the shortcomings of the prior art, such as changes in output waveform due to wave number, can be easily improved and minimized.
第1図は本発明の一実施例の平面図、第2図は従来の一
例でめる1/2分周器の平面図、第3図は第2図の1/
2分周器における出力波形モニタ図でめる。
1・・・・・・入力パッド、2・・・・・・1/2分周
器回路部、3・・・・・・半絶縁性ひ化ガリウム基板、
4・・・・・・出力パラド、5・・・・・・出力信号1
!2絖線、6・・・・・・接地用環体。
竿 ! 図
$ 2 図
芽3 面Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a plan view of a conventional 1/2 frequency divider, and Fig. 3 is a 1/2 frequency divider of Fig. 2.
The output waveform monitor diagram of the 2 frequency divider is shown. 1...Input pad, 2...1/2 frequency divider circuit section, 3...Semi-insulating gallium arsenide substrate,
4... Output parad, 5... Output signal 1
! 2 wires, 6...Grounding ring. Rod! Figure $ 2 Figure 3 side
Claims (1)
積回路への入出力端子用パッド及び入出力信号接続線を
有する半導体装置において、前記集積回路、入出力端子
用パッドおよび入出力信号線の周囲に接地用導体を設け
たことを特徴とする半導体装置。In a semiconductor device having an integrated circuit formed on a semi-insulating semiconductor substrate, an input/output terminal pad, and an input/output signal connection line to the integrated circuit, the integrated circuit, the input/output terminal pad, and the input/output signal line are A semiconductor device characterized in that a grounding conductor is provided around the periphery.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22171284A JPS61100955A (en) | 1984-10-22 | 1984-10-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22171284A JPS61100955A (en) | 1984-10-22 | 1984-10-22 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61100955A true JPS61100955A (en) | 1986-05-19 |
JPH0481864B2 JPH0481864B2 (en) | 1992-12-25 |
Family
ID=16771084
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22171284A Granted JPS61100955A (en) | 1984-10-22 | 1984-10-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61100955A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62291976A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | High-frequency semiconductor device |
US4924290A (en) * | 1987-08-31 | 1990-05-08 | Kabushiki Kaisha Toshiba | Semiconductor device having improved multilayered wirings |
US5194932A (en) * | 1990-05-30 | 1993-03-16 | Nec Corporation | Semiconductor integrated circuit device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
JPS5586360U (en) * | 1978-12-12 | 1980-06-14 | ||
JPS5853845A (en) * | 1981-09-26 | 1983-03-30 | Fujitsu Ltd | Semiconductor integrated circuit |
-
1984
- 1984-10-22 JP JP22171284A patent/JPS61100955A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
JPS5586360U (en) * | 1978-12-12 | 1980-06-14 | ||
JPS5853845A (en) * | 1981-09-26 | 1983-03-30 | Fujitsu Ltd | Semiconductor integrated circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62291976A (en) * | 1986-06-12 | 1987-12-18 | Matsushita Electric Ind Co Ltd | High-frequency semiconductor device |
US4924290A (en) * | 1987-08-31 | 1990-05-08 | Kabushiki Kaisha Toshiba | Semiconductor device having improved multilayered wirings |
US5194932A (en) * | 1990-05-30 | 1993-03-16 | Nec Corporation | Semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
JPH0481864B2 (en) | 1992-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS61100955A (en) | Semiconductor device | |
JPS61234055A (en) | Semiconductor device | |
JP3157547B2 (en) | Semiconductor package | |
JPH0380601A (en) | Microwave converting circuit | |
US6646343B1 (en) | Matched impedance bonding technique in high-speed integrated circuits | |
JPH0423827B2 (en) | ||
JPH03211870A (en) | Monolithic microwave integrated circuit | |
JP2637975B2 (en) | Package for semiconductor device | |
JPS61104673A (en) | Fet device for ultrahigh frequency | |
JPH02291140A (en) | Ultrahigh-frequency band mounting structure | |
JPH0969604A (en) | Method and circuit for impedance matching | |
JPH054281Y2 (en) | ||
JPS62156848A (en) | Chip carrier | |
JP2725317B2 (en) | Resin-sealed semiconductor device | |
JPS61172376A (en) | Semiconductor device | |
JPH05190609A (en) | Tape carrier for tab | |
JPS63203001A (en) | Semiconductor device | |
JPH03211842A (en) | Mounting structure of ic chip | |
JPH04278570A (en) | Lead frame for ic use | |
JP2720481B2 (en) | Semiconductor device | |
JPH02107001A (en) | High frequency circuit device | |
JPS62150902A (en) | Earth structure for microwave integrated circuit parts | |
JPS62291202A (en) | Microstrip circuit | |
JPH04109701A (en) | Microwave semiconductor device | |
JPH01239945A (en) | Hybrid integrated circuit device |