JPS6094738A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPS6094738A JPS6094738A JP20347583A JP20347583A JPS6094738A JP S6094738 A JPS6094738 A JP S6094738A JP 20347583 A JP20347583 A JP 20347583A JP 20347583 A JP20347583 A JP 20347583A JP S6094738 A JPS6094738 A JP S6094738A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon
- parts
- type
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は、半導体基板に関するものである。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a semiconductor substrate.
一般に、半導体基板は、つぎのような２種類の方法によ
り製造されている。すなわち、第１の方法は、第１図に
示すように、単結晶シリコン１を図示のようにエツチン
グしたのち、第２図に示すように、その表面の全体を酸
化して酸化膜２を形（１）
成し、ついでその酸化膜２の上に、第３図に示すように
、ポリシリコン３を堆積させ、これを単結晶シリコン１
１ｕｌ＋から鎖線Ａで示す位置まで研磨し、かつポリシ
リコン３の表面４を平坦化するという方法であ乞。この
ようにして得られたものを、上下を逆−して第４図に示
す。すなわち、この半導体基板は、ポリシリコン基板３
の表面に酸化膜２で囲われた中結晶シリコン部（素子形
成部）１が形成されており、素子形成部１が酸化膜２で
絶縁分離された構造になっている。ところが、このよう
にして半導体基板を製造する場合には、第３図に示すポ
リシリコン３の表面の凹凸４が激しい状態となっている
ため、これを研磨等により平坦化し第４図に示すような
状態にしなければならない。したがって、その研磨等に
要する手間がかかるという問題があった。Generally, semiconductor substrates are manufactured by the following two types of methods. That is, in the first method, as shown in FIG. 1, a single crystal silicon 1 is etched as shown, and then, as shown in FIG. 2, the entire surface is oxidized to form an oxide film 2. (1) Then, on the oxide film 2, as shown in FIG.
The method is to polish from 1ul+ to the position shown by the chain line A, and to flatten the surface 4 of the polysilicon 3. The product thus obtained is shown in FIG. 4, upside down. That is, this semiconductor substrate is a polysilicon substrate 3.
A medium-crystalline silicon portion (element forming portion) 1 surrounded by an oxide film 2 is formed on the surface of the substrate, and the element forming portion 1 is insulated and isolated by the oxide film 2. However, when manufacturing a semiconductor substrate in this way, since the surface of the polysilicon 3 shown in FIG. 3 has severe unevenness 4, this is flattened by polishing or the like, as shown in FIG. must be in good condition. Therefore, there has been a problem in that polishing and the like are time-consuming.
第２の方法は、Ｐ形シリコン基板５の表面側のとごろど
ころにＮ型領域６を第５図に示すように形成し、このＮ
型領域６が形成されたシリコン基板５を第６図に示すフ
ッ酸陽極反応装置にかける。The second method is to form N-type regions 6 here and there on the surface side of a P-type silicon substrate 5 as shown in FIG.
The silicon substrate 5 on which the mold region 6 has been formed is placed in a hydrofluoric acid anode reaction apparatus shown in FIG.
（２）
第６図において、５はシリコン基板であり、そのＮ型領
域形成面５ａが内側に向けられている。そしてこのシリ
コン基板５が直流電源７のプラス側に接続され、マイナ
ス側に陰極電極８が接続され、このシリコン基板５と陰
極電極８との間に電流を流すことによりシリコン基板５
のＮ影領域形成面５ａ側を多孔質化するのである。９は
フッ酸溶液である。このようにしてフッ酸陽極反応を終
えた状態のシリコン基板５は、第７図に示すようにＮ型
領域６とＮ型領域６の間の部分が多孔質シリコン部１０
となっている。このような多孔質シリコン部１０を備え
たシリコン基板５を、酸化処理すると、多孔質シリコン
部１０が酸化され、第８図に示すように二酸化シリコン
部１０ａとなるため、Ｎ型領域６が二酸化シリコン部１
０ａにより絶縁分離される。その結果、二酸化シリコン
部１０ａにより絶縁分離されたＮ型領域（素子形成部）
６を有する半導体基板が得られる。ところが、このよう
にして半導体基板を製造する場合には、Ｎ型領域６が浅
くて狭いときはよいが、Ｎ型領域（３）
６が深いか、もしくは広くなると多孔質化に非常に長時
間を要するようになる。すなわち、多孔質化は、フッ酸
陽極化反応がＮ型領域６とＮ型領域６の間からシリ：１
ン基板５の内部に進むことによってＮ型領域６の両側か
らＮ影領域６に沿って下の方に延び、Ｎ型領域６の下側
で繋がった状態になるように生じる。そのため、Ｎ影領
域６が深いか、もしくは広いと多孔質化に非常に長時間
を要するのである。(2) In FIG. 6, 5 is a silicon substrate, and its N-type region forming surface 5a is directed inward. This silicon substrate 5 is connected to the plus side of the DC power supply 7, and the cathode electrode 8 is connected to the minus side, and by passing a current between the silicon substrate 5 and the cathode electrode 8, the silicon substrate
The N shadow area forming surface 5a side is made porous. 9 is a hydrofluoric acid solution. After the hydrofluoric acid anodic reaction has been completed, the silicon substrate 5 has a porous silicon portion 10 in the portion between the N-type regions 6, as shown in FIG.
It becomes. When the silicon substrate 5 having such a porous silicon portion 10 is oxidized, the porous silicon portion 10 is oxidized and becomes a silicon dioxide portion 10a as shown in FIG. Silicon part 1
They are insulated and separated by 0a. As a result, an N-type region (element forming part) isolated by the silicon dioxide part 10a
6 is obtained. However, when manufacturing a semiconductor substrate in this way, it is good if the N-type region 6 is shallow and narrow, but if the N-type region (3) 6 is deep or wide, it will take a very long time to become porous. It becomes necessary to That is, the formation of porosity is caused by the hydrofluoric acid anodization reaction, which causes silica:1 to form between the N-type regions 6 and 6.
By proceeding into the inside of the N-type substrate 5, the N-type region 6 extends downward along the N-shaded region 6 from both sides of the N-type region 6, and is formed so as to be connected below the N-type region 6. Therefore, if the N shadow region 6 is deep or wide, it takes a very long time to make it porous.
〔発明のＩ−１的］
この発明は、絶縁分離された素子形成部をもつ半導体基
板の製造時間の短縮化を目的とするものである。[I-1 aspect of the invention] The present invention aims to shorten the manufacturing time of a semiconductor substrate having an insulated element forming portion.
この発明は、シリコン基板の表面層の一部が素子形成部
に形成され、この素子形成部の底部がシリコン酸化膜で
シリコン基板の内部と区切られているとともに、素子形
成部の側部が全周にわたって二酸化シリコン層で囲われ
ていて素子形成部がシリコン酸化膜および二酸化シリコ
ン層で絶縁分（４）
離されていることを特徴とする半導体基板をその要旨と
するものである。In this invention, a part of the surface layer of the silicon substrate is formed in the element forming part, the bottom part of the element forming part is separated from the inside of the silicon substrate by a silicon oxide film, and the side part of the element forming part is completely covered. The gist of this semiconductor substrate is that it is surrounded by a silicon dioxide layer over its periphery, and has an element forming portion separated by an insulating distance (4) between a silicon oxide film and a silicon dioxide layer.
すなわち、この半導体基板は、上記のように素子形成部
の底部がシリコン酸化膜で他の部分と区別され、かつ側
部の全周が二酸化シリコン層で囲われた構造になってい
て素子形成部の絶縁分離が容易にできるようになってい
るため、製造の短縮化が実現できるようになる。In other words, as described above, this semiconductor substrate has a structure in which the bottom of the element forming area is separated from other parts by a silicon oxide film, and the entire periphery of the side area is surrounded by a silicon dioxide layer. Since the insulation separation can be easily performed, manufacturing can be shortened.
つぎに、この発明を実施例にもとづいて詳しく説明する
。Next, the present invention will be explained in detail based on examples.
すなわち、Ｐ形シリコン基板の表面を熱酸化して５ｉ０
２膜を形成し、第９図に示すように、このＰ形シリコン
基板５の素子形成部に対応する５ｉ０２膜の部分２ａの
みを残し、他の５ｉ０２膜の部分を除去する。つぎに、
そのＰ形シリコン基板５に対してエピタキシャル成長を
施すと、第１０図に示すように、Ｐ形シリコン基板５の
上にエピタキシャル成長層１２が形成される。この場合
、５ｉ０２膜２ａの上の部分１３はポリシリコンとなる
。つぎに、第１０図の状態のものを上下を（５）
逆にし、■）形シリコン基板５の側を第１１図に示す６
１、うに研磨し、必要とする素子形成単結晶の深さにす
る。一つぎにその素子形成部１３ａに対応するシリコン
Ｗ扱５の表面部分に対して酸化膜（図示セず）でマスク
を施し、これを第６図に示すようなフ・ン酸陽極反応装
置にかけて反応させ、素子形成部１３；Ｊの周囲のシリ
コン基板５の部分を多孔質化する。つぎにマスクを取り
除き、酸化処理を施すと、そのフッ酸陽極反応により形
成された多孔質シリコン部が第１２図に示すように、陽
極酸化による二酸化シリコン部１１となり、素子形成部
１３ａの全周がこの二酸化シリコン部１１により囲われ
た状態となる。That is, the surface of the P-type silicon substrate is thermally oxidized to form 5i0
As shown in FIG. 9, only a portion 2a of the 5i02 film corresponding to the element formation portion of this P-type silicon substrate 5 is left, and the other 5i02 film portions are removed. next,
When epitaxial growth is performed on the P-type silicon substrate 5, an epitaxial growth layer 12 is formed on the P-type silicon substrate 5, as shown in FIG. In this case, the upper portion 13 of the 5i02 film 2a becomes polysilicon. Next, turn the one in the state shown in FIG. 10 upside down (5), and turn the 6
1. Polish to the required depth of the element-forming single crystal. Next, a surface portion of the silicon W material 5 corresponding to the element forming portion 13a is masked with an oxide film (not shown), and this is applied to a fluoric acid anode reaction apparatus as shown in FIG. A reaction is caused to make the portion of the silicon substrate 5 around the element forming portion 13; J porous. Next, when the mask is removed and oxidation treatment is performed, the porous silicon portion formed by the hydrofluoric acid anodic reaction becomes a silicon dioxide portion 11 by anodization, as shown in FIG. is surrounded by this silicon dioxide portion 11.
このよ・うにＬ７て目的とする半導体基板が得られる。In this way, the desired semiconductor substrate L7 is obtained.
この半導体基板ば、素子形成部１３ａの下側が熱酸化に
より得られた５ｉ０２Ｉｉ２ａで絶縁され、側面が陽極
酸化により得られた二酸化シリコン部１１で絶縁された
構造となっている。このように、この半導体基板は、従
来のようなポリシリコン部の表面を研磨して平坦化する
というような（６）
ことが不要となり、また素子形成部１３ａがどのように
広くなっても、フッ酸陽極反応を行う時間が一定かつ短
時間になるため製造時間の短縮化をはかることができる
。すなわち、上記の二酸化シリコン部１１は、素子形成
部１３ａの側面を絶縁するにたりる深さ分だけ形成すれ
ばよく、従来のように素子形成部１３ａの下側にまで入
り込ませる必要がないため、素子形成部１３ａがどのよ
うな広さになっても一定の深さだけ形成すればたりるよ
うになる。その結果、製造時間の短縮化が実現しうるよ
うになり、この効果と上記ポリシリコン部の平坦化の不
要効果とが相俟って製造時間の著しい短縮化を実現しう
るようになるのである。This semiconductor substrate has a structure in which the lower side of the element forming portion 13a is insulated with 5i02Ii2a obtained by thermal oxidation, and the side surface is insulated with silicon dioxide portion 11 obtained by anodic oxidation. In this way, this semiconductor substrate does not require the conventional polishing and flattening of the surface of the polysilicon portion (6), and no matter how wide the element forming portion 13a becomes, Since the time for performing the hydrofluoric acid anodic reaction is constant and short, the manufacturing time can be shortened. That is, the silicon dioxide portion 11 need only be formed to a depth sufficient to insulate the side surface of the element forming portion 13a, and does not need to penetrate to the bottom of the element forming portion 13a as in the conventional case. , no matter how wide the element forming portion 13a becomes, it will be sufficient if it is formed to a certain depth. As a result, it becomes possible to shorten the manufacturing time, and this effect, combined with the above-mentioned effect of not requiring planarization of the polysilicon portion, makes it possible to realize a significant reduction in the manufacturing time. .
なお、−り記の実施例では、フッ酸陽極化反応に際して
素子形成部１３ａの表面を酸化膜でマスクしているが、
それに変えて素子形成部１３ａをＮ型領域化しておいて
フッ酸陽極化反応を施してもよい（フッ酸陽極化反応は
Ｎ形部分には及ばない）。上記のような絶縁分離法は、
Ｃ−ＭＯＳまたは集積太陽電池に応用しうるものである
。In addition, in the embodiment described above, the surface of the element forming portion 13a is masked with an oxide film during the hydrofluoric acid anodization reaction.
Alternatively, the element forming portion 13a may be made into an N-type region and subjected to a hydrofluoric acid anodization reaction (the hydrofluoric acid anodization reaction does not affect the N-type region). The above insulation separation method is
It can be applied to C-MOS or integrated solar cells.
（７）
〔発明の効Ｗ〕
以上のように、この発明の半導体基板は、シリコン基板
の素子形成部の下側部分にシリコン酸化膜が形成され、
かつシリコン基板の素子形成部の側部が全周にわた−っ
て二酸化シリコン部で囲まれ、それによって素子形成部
が絶縁分離された構造であるため、製造に際して従来の
ようにポリシリコンの表面を甲Ｊ」１化するということ
が不必要となる。また、二酸化シリコン部も素子形成部
の間の狭い部分にのみ形成すれば足りるため、従来のよ
うに広い二酸化シリコン部の形成が不必要となる。した
がって、ｇＡ造待時間著しい短縮化を実現しうるように
なる。(7) [Effect W of the Invention] As described above, in the semiconductor substrate of the present invention, a silicon oxide film is formed on the lower part of the element formation portion of the silicon substrate,
In addition, the side part of the element formation area of the silicon substrate is surrounded by silicon dioxide over the entire periphery, and the element formation area is insulated and isolated. It becomes unnecessary to make it ``1''. Further, since it is sufficient to form the silicon dioxide portion only in a narrow portion between the element formation portions, it is unnecessary to form a wide silicon dioxide portion as in the conventional case. Therefore, it is possible to significantly shorten the gA production waiting time.
なお、フッ酸陽極化反応を利用して絶縁分離する方法で
は、二酸化シリコンの絶縁層が厚く形成される（第８図
参照）ため製造時間の長期化だけでなく基板の反り歪み
等が生じるという問題がある。このような反り歪みを解
消する方法としてっぎのような２種Ｉｎの方法がある。In addition, in the method of isolation using a hydrofluoric acid anodization reaction, a thick silicon dioxide insulating layer is formed (see Figure 8), which not only lengthens the manufacturing time but also causes warping and distortion of the substrate. There's a problem. As a method for eliminating such warping distortion, there is a two-type In method such as the one described above.
（８）
第１の方法は、つぎのとおりである。すなわち、第１３
図に示すようにＮ型エピタキシャル層１４を備えたＰ形
シリコン基板５を準備し、このＰ形シリコン基板５に対
してそのエピタキシャル層１４側から選択的にＰ形不純
物（ポロン）をＰ形シリコン基板５の上面に達するまで
拡散させ、第１４図に示すように、エピタキシャル成長
Ｎ１４内にＰ影領域１５を部分的に形成する。つぎに第
１５図に示すように、その形成されたＰ影領域１５内に
Ｎ型不純物（リン）を拡散し、Ｐ影領域１５内にＮ型領
域１６を形成する。つぎにこれを第６図に示すようなフ
ッ酸陽極化反応装置にかけてフッ酸陽極化反応を施すと
、第１６図に示すようにＰ影領域１５内の残存Ｐ形部分
だけが多孔質シリコン化され多孔質シリコン部１０とな
る。（フッ酸陽極化反応はＰ形にのみ選択的に反応する
）つぎにこれを酸化雰囲気中（酸素または水蒸気）に入
れて酸化すると多孔質シリコン部１０が二酸化シリコン
部１１となり、それによってＮ型領域１６が絶縁分離さ
れる。第１７図において、１７は酸（９）
化雰囲気中に入れることによって生成した酸化膜である
。(8) The first method is as follows. That is, the 13th
As shown in the figure, a P-type silicon substrate 5 having an N-type epitaxial layer 14 is prepared, and a P-type impurity (poron) is selectively added to the P-type silicon substrate 5 from the epitaxial layer 14 side. It is diffused until it reaches the upper surface of the substrate 5, and as shown in FIG. 14, a P shadow region 15 is partially formed in the epitaxial growth N14. Next, as shown in FIG. 15, an N type impurity (phosphorus) is diffused into the formed P shadow region 15 to form an N type region 16 within the P shadow region 15. Next, when this is subjected to a hydrofluoric acid anodization reaction in a hydrofluoric acid anodization reaction apparatus as shown in FIG. 6, only the remaining P type portion in the P shadow area 15 becomes porous silicon as shown in FIG. This forms a porous silicon portion 10. (The hydrofluoric acid anodization reaction selectively reacts only with the P type.) Next, when this is placed in an oxidizing atmosphere (oxygen or water vapor) and oxidized, the porous silicon part 10 becomes the silicon dioxide part 11, and thereby the N type Region 16 is isolated. In FIG. 17, 17 is an oxide film formed by placing the material in an acid (9) atmosphere.
このように、この例によれば、多孔質シリコン部１０が
形成される領域が、Ｐ影領域１５内における狭い部分で
あるため、その酸化によって形成される二酸化シリコン
部１１も狭くなり、そのため基板５の反りや歪みが減少
するようになる。As described above, according to this example, since the region where the porous silicon portion 10 is formed is a narrow portion within the P shadow region 15, the silicon dioxide portion 11 formed by the oxidation is also narrow, so that the substrate 5. Warpage and distortion will be reduced.
基板５に対する反りや歪みを低減させる第２の方法はつ
ぎのとおりである。すなわち、第１８図に示すようにＮ
型領域１６が選択的に形成されたＰ形シリコン基板５を
準備する。つぎにこのＰ形シリコン基板５を第１９図に
示すようなフッ酸陽極反応装置にかける。第１９図にお
いて、５はＰ形シリコン基板、１８はテフロン製容器、
９はその容器内に満たされたフッ酸溶液、１９はｐｔ電
極でシリコン基板５の表面および裏面に対面するように
２個設けられている。２ｏは０リング、７はそれぞれ直
流電源であり、切換スイッチ７ａにより矢印のように切
り換え得るｆうになっている。すなわち、Ｐ形シリコン
基板５をこ（７）７ツＭ陽（１０）
極反応装置にかけ、切換スイッチ７ａを一定時間ごとに
切り換えることにより、Ｐ形シリコン基板５の両面にフ
ッ酸陽極反応が施される。その結果、第２０図に示すよ
うにＰ形シリコン基板５の表面および裏面がそれぞれ多
孔質シリコン部１０となる。つぎにこれを酸化雰囲気（
酸素または水蒸気）に入れて酸化処理することにより、
上記多孔質シリコン部ＩＯが第２１図に示すように二酸
化シリコン部１１となり、その二酸化シリコン部１１に
より、Ｎ型領域１６が絶縁分離される。１７は酸化によ
り生成される酸化膜である。A second method for reducing warpage and distortion on the substrate 5 is as follows. That is, as shown in FIG.
A P-type silicon substrate 5 on which mold regions 16 are selectively formed is prepared. Next, this P-type silicon substrate 5 is placed in a hydrofluoric acid anode reaction apparatus as shown in FIG. In FIG. 19, 5 is a P-type silicon substrate, 18 is a Teflon container,
9 is a hydrofluoric acid solution filled in the container, and 19 is a PT electrode, two of which are provided so as to face the front and back surfaces of the silicon substrate 5. 2o is an O ring, and 7 is a DC power source, which can be switched as shown by the arrow by a changeover switch 7a. That is, by applying the P-type silicon substrate 5 to this (7)7M anode (10) electrode reaction device and switching the changeover switch 7a at regular intervals, a hydrofluoric acid anodic reaction is performed on both sides of the P-type silicon substrate 5. be done. As a result, as shown in FIG. 20, the front and back surfaces of the P-type silicon substrate 5 each become a porous silicon portion 10. Next, this is placed in an oxidizing atmosphere (
By oxidizing it by putting it in oxygen or water vapor),
The porous silicon portion IO becomes a silicon dioxide portion 11 as shown in FIG. 21, and the N-type region 16 is insulated and isolated by the silicon dioxide portion 11. 17 is an oxide film produced by oxidation.
この例によれば、シリコン基板５の表面および裏面にそ
れぞれ二酸化シリコンの絶縁１ｉｉ１１が形成されるた
め、その両層１１により、反りや歪みが相殺され、シリ
コン基板５の反りや歪みが全体的に防止されるようにな
る。According to this example, since the silicon dioxide insulation 1ii11 is formed on the front and back surfaces of the silicon substrate 5, both layers 11 cancel out the warpage and distortion, and the warpage and distortion of the silicon substrate 5 are minimized as a whole. will be prevented.
【図面の簡単な説明】
第１図ないし第４図は従来例の説明図、第５図ないし第
８図は他の従来例の説明図、第９図ないし第１２図はこ
の発明の一実施例の製造説明図、（１１）
第１３図ないし第１７図は基板に対する反りや歪みの発
生を防ｌトする例の説明図、第１８図ないし第２１．図
は基板番□二対する反りや歪みの発生を防止する他の例
の説明図である。
２ａ・・・酸化１１襲 ５・・・１）形シリコン基板
１１・・・二酸化シリコン部 １３ａ・・・素子形成部
代理人 弁理士 松 本 武 彦
（１２）
第５図
７
８ −ヨテー ９
ａ
−＝５
第９図
第１０図
第６図
第８図
第１１図
第１２図
第１３図
第１４図
第１５図
第１９図
棺ワへ闘
第１７図
弔ｌＵ凶
第２１図[Brief Description of the Drawings] Figures 1 to 4 are explanatory diagrams of a conventional example, Figures 5 to 8 are explanatory diagrams of other conventional examples, and Figures 9 to 12 are illustrations of an embodiment of the present invention. (11) FIGS. 13 to 17 are explanatory views of examples of preventing warping and distortion of the substrate, and FIGS. 18 to 21. The figure is an explanatory diagram of another example of preventing the occurrence of warpage and distortion on the board number □2. 2a... Oxidation 11 attack 5...1) type silicon substrate
11...Silicon dioxide part 13a...Element formation department agent Patent attorney Takehiko Matsumoto (12) Fig. 5 7 8 -Yote 9 a -=5 Fig. 9 Fig. 10 Fig. 6 Fig. 8 Figure 11Figure 12Figure 13Figure 14Figure 15Figure 19Fight to the CoffinFigure 17 Condolence Figure 21
Claims (1)
形成され、この素子形成部の底部がシリコン酸化膜でシ
リコン基板の内部と区切られているとともに、素子形成
部の側部が全周にわたって二酸化シリコン層で囲われて
いて素子形成部がシリコン酸化膜および二酸化シリコン
層で絶縁分離されていることを特徴とする半導体基板。fl, l A part of the surface layer of the silicon substrate is formed in the element formation part, and the bottom of this element formation part is separated from the inside of the silicon substrate by a silicon oxide film, and the side part of the element formation part is formed on the entire periphery. What is claimed is: 1. A semiconductor substrate characterized in that the semiconductor substrate is surrounded by a silicon dioxide layer over the entire length and has an element formation portion insulated and isolated by a silicon oxide film and a silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20347583A JPS6094738A (en) | 1983-10-28 | 1983-10-28 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20347583A JPS6094738A (en) | 1983-10-28 | 1983-10-28 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6094738A true JPS6094738A (en) | 1985-05-27 |
Family
ID=16474753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20347583A Pending JPS6094738A (en) | 1983-10-28 | 1983-10-28 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6094738A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125039A (en) * | 1984-11-21 | 1986-06-12 | Nec Corp | Semiconductor device and manufacture thereof |
| JPS61284934A (en) * | 1985-06-10 | 1986-12-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device having element separating insulating layer |
| US4680963A (en) * | 1985-01-24 | 1987-07-21 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor flow velocity sensor |
| JP2009508323A (en) * | 2005-06-27 | 2009-02-26 | ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア | Method for forming shallow grooves |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50120280A (en) * | 1974-03-05 | 1975-09-20 |
-
1983
- 1983-10-28 JP JP20347583A patent/JPS6094738A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50120280A (en) * | 1974-03-05 | 1975-09-20 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125039A (en) * | 1984-11-21 | 1986-06-12 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH0478178B2 (en) * | 1984-11-21 | 1992-12-10 | Nippon Electric Co | |
| US4680963A (en) * | 1985-01-24 | 1987-07-21 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Semiconductor flow velocity sensor |
| JPS61284934A (en) * | 1985-06-10 | 1986-12-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device having element separating insulating layer |
| JP2009508323A (en) * | 2005-06-27 | 2009-02-26 | ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア | Method for forming shallow grooves |
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