JPS6091885A - Speed control circuit for motor - Google Patents

Abstract

PURPOSE:To control the speed of a motor which has low power consumption by detecting the phase difference between a signal of a motor frequency generator and a reference clock corresponding to the target speed and controlling the power by the phase difference signal, thereby limiting the excess supply power. CONSTITUTION:A phase detector 3 outputs a phase difference signal between a reference clock phiS and the frequency signal phiM of a motor 5. An AND gate 12 extracts the superposed portion between the output Q3 of a memory 11 showing that the previous signal phiM is earlier than the prescribed time and the output Q2 of a memory 10 showing that the present symbol phiM is delayed from the prescribed time, and passes the 75% duty command signal from a coefficient generator 9. An OR gate 16 applies the output of the detector 3 when the AND gate 12 produces no output and the output of the generator 9 when the gate 12 produces an output to the motor 5 through an amplifier 4.

Description

[Detailed Description of the Invention] [Technical Field] The present invention supplies energizing power using a phase difference signal from a phase detector that detects the phase difference between a signal from a motor frequency generator and a standard clock corresponding to a target speed of the motor. [Prior art] A conventional motor speed control circuit related to the present invention will be explained with reference to Fig. 6 and Fig. 7. . In FIG. 6, 1 is an oscillator which generates a reference clock φ. 2 is a counter that receives a clock φ at a clock input terminal OL, divides the frequency, and outputs a standard clock φB corresponding to the target speed of the motor from a carry terminal Oa. Reference numeral 6 denotes a phase detector, and in the figure, it is shown as a reset set-flip 70-tube (hereinafter referred to as R8-FF) of the usual concept.

When the four-wheel drive φ8 is input to the set terminal 8, the output terminal Q
1 are arranged in a row. The Q1 output opens and closes the amplifier 4 and energizes the motor 5. 6 is a frequency generator (hereinafter referred to as FG) that generates a frequency proportional to the speed of the motor 5, and the frequency signal is φM.

The signal φM is input to the reset terminal of R8-Irag and turns off the Q1 output. That is, the phase difference between the clock φS and the signal φM is the Q1 output. The speed of the motor 5 is controlled in a closed loop in which the motor 5 is energized at the cycle of clock φ8 using the time width of this phase difference. Since the motor speed control circuit shown in FIG. 6 is simple and the amplifier 4 operates in a switching manner, the power consumption of the amplifier 4 itself is extremely low.

Next, an example of the operation of the circuit shown in FIG. 6 will be explained. In FIG. 7, the period of clock φ8 is indicated by T. Four examples of signal φM and Q1 output are shown with a subscript added to P.

When φMl and Pl are moderately loaded, φM and P.

indicates a case where the load is smaller than the case of φM1 and P, and pM and Ps indicate the case where the load is larger than the case of φM and P. These three examples show that the time duration for energizing the motor 5 is adjusted according to the load, and the motor 5 rotates at a smooth constant speed.

However, in the conventional motor speed control circuit shown in FIG. 6, rotational irregularities with a period of 2T indicated by φM4 and P4 often occur. There are many cases where this occurs, such as when there is a large load change corresponding to the load P from the load P, or when the cycle of the clock φ8 is changed to switch from high speed to low speed operation. Possible solutions include increasing the inertia of the motor 5 to increase the time constant of the system, and minimizing the power supply capacity so that the phase difference is 100% at maximum load. Increasing the inertia of the motor 5 has the drawback that, for example, the vertical-E characteristic for reaching a predetermined target speed from a stopped state deteriorates. Adjusting the power supply capacity is good for equipment with small load fluctuations, but it has a drawback that limits its application.

In any case, the cause is that once a large amount of power is supplied, the motor 5 is over-accelerated, and in the next cycle, the power is automatically reduced, resulting in a power shortage, and the rotation is over-decreased, causing the next The signal φM is delayed and the period of energization is extended, and a large amount of power is supplied again, causing uneven rotation with a period of 2T.

The present invention aims to eliminate this cause and obtain a control circuit that is stable over a wide range.

〔the purpose〕

The purpose of the present invention is to provide stable low power consumption by adding a circuit for detecting an unstable state in a closed loop speed control circuit that energizes a motor based on the phase difference between a standard clock and a motor FG signal. The present invention provides a motor speed control circuit. Another object of the present invention is to provide a motor speed control circuit which simplifies the logic configuration of additional circuitry for stabilizing the system. Still another object of the present invention is to achieve the above-mentioned object, thereby facilitating the integration of a speed control circuit alone or in combination with other functions onto a substrate such as silicon (hereinafter referred to as process 0). The purpose is to provide a control circuit.

〔Example〕

FIG. 1 shows one embodiment of a motor speed control circuit according to the present invention. If switch 7 is turned to the Q1 side in FIG. 1, the same operation as in FIG. 6 will occur. A counter 8 has the same capacity as the counter 2 and counts the clock φ, and is reset every time the signal φM arrives, so that the count becomes zero. When the total count is completed, the carry is released from the carry terminal. Reference numeral 9 denotes a coefficient generator composed of, for example, a decoder, which generates a pulse waveform with a duty of 75% using the lower two bits of the n1 counter 8. When a pulse waveform with an even smaller width is to be generated, it is generated in cooperation with the oscillator 1.

10 is a memory circuit composed of D-7 lip-flops;
The input terminal is at a logic level high (indicated by H in the figure. In the following, logic levels may also be referred to as H and L). If the time interval of the signal φM is longer than the predetermined time, the terminal OL receives the discharge of the carry from the counting book 8, and the output continues until the next signal φM arrives. Reference numeral 11 denotes a memory circuit composed of D-7 flip-flops like the i-pin memory circuit 10. The D input is connected to each other and the output of the memory circuit, and the OL terminal is connected to the signal φM. When connected in this way, the second output of the memory circuit 10 is H if the signal φM comes earlier than the predetermined time, so the memory circuit 11
The Q, output of outputs H and continues until the next signal φM arrives and the state of the D input changes. Reference numeral 12 is an AND gate that extracts the overlapping portion of the Q3 output, which indicates that the previous signal φM was earlier than the predetermined time, and Q, which indicates that the current signal φM is delayed than the predetermined time. AN
The D gate 14 is set to 1 to allow the signal from the coefficient generator 9 to pass. When there is no output from the AND gate 12, the inverter 13 passes the Q1 output of the phase detector 6 by υd through the AND gate 15. The outputs of AND gates 14 and 15 are applied via OR gate 16 to amplifier 4 via switch 7 through line 16α.

Next, an example of the operation shown in FIG. 1 will be explained with reference to FIG. Assume that before the switch 7 was set to the line 16α side, large rotational irregularities were occurring as shown in the diagram indicated by Ql. The memory circuit 11 receives the FG signal φ
The operation time chart of each part is shown below, indicated as φM in FIG. 3, for the case where the switch 7 is set to the line 16α side after detecting that M is earlier than the predetermined time. The output Q becomes H after 7 hours, and the AND gate 12 becomes H, allowing the signal from the coefficient generator 9 to pass. At this time, the AND gate 15 secures the previous energized state, the AND gate 14 outputs the cut energized state, and the synthesized result appears on the line 16α. If this is done, the power supplied to the motor 5 will be reduced, so that the next signal φM will be delayed. If this is delayed, the next signal φM is further delayed. In this case, the phase difference of the new phase detector is Q
', the periodic unbalanced power supplied to the motor 5 is corrected and averaged. The AND gate 14 has the role of a damping coefficient when the speed is controlled in a closed loop using a continuous time signal.

In the end, since only the signal passing through the AND gate 15 remains, the signal of W 16 a becomes the same as the QI output of the phase detector 6. What is marked as δ in the diagram of FIG. 6 means a small amount.

Next, another embodiment of the motor speed control circuit according to the present invention will be explained with reference to FIG. In the embodiment of the present invention shown in FIG. 1, the control signal has a notch and has many high frequency components, which may cause radio wave interference, so a continuous pulse control signal is used, although it is somewhat expensive.

In Fig. 2, 19 is an example of dividing the count contents of the counter 8.
It is a decoder that classifies. 18 is a coefficient generator with different widths, which corresponds to the number of decoders 19. 20 is a storage circuit consisting of two D-7 flip-flops, and output Q, and Q6 are A
It becomes an input to ND gates 22 and 21. AND gate 21
and 22 have the same role as the AND gate 14 in FIG.

26 is an OR gate and AND gate 15, 22, 3 of 21
It is human power.

If the FG signal φM is early, the AND gate 24 outputs φ
The data from the decoder 19 is taken into the storage circuit 20 by passing through the decoder M. If the FG signal φM is slow, the AND gate 25 allows φM to pass through and resets the memory circuit 20.

Next, an example of the operation shown in FIG. 2 will be explained with reference to FIGS. 4 and 5. In the figure, the case will be explained in which the switch 7 is set to Qlffl of the phase detector 6.

In FIG. 4, Q9 of the decoder 19 is, for example, the signal φ of the FG.
It is designed to be output when the time interval of M is less than /2T. At this time, since the signal φM passes through the AND gate 24, Q of the memory circuit 20 becomes H. AND gate 12
The trailing edge of Ql is the same as the trailing edge of Ql, but the coefficient generator 18 ends before it, so it is deleted and the result is AND gate 15.
The passing portion and ANDN-gate 2 passing portion are shown at 16α. If a part of the current-carrying wire with a wide width of the original Ql is cut and the loop is closed, the speed of the motor 5 will drop and the next signal φM will be delayed, and the next signal φM will be delayed as shown in Figure 1. is late and thin Q
, to correct the power supply irregularity with a period of 2T.

FIG. 5 shows Ql of the decoder 19 when τ is 1/2T>τ>0. This is how it is output. Coefficient generator 18 glue,
is determined to be 1/4T width in the diagram, so AND gate 1
The output of 2 1/4T or more is deleted and the AND gate 21 outputs it.

In this way, the relationship between the pulse widths of the coefficient generator 18 is stored in the memory circuit 2.
If the signal φM of 0 is matched to the range where the signal τ earlier than the predetermined time T is divided, the same effect as in FIG. 1 will be obtained.

In this case, the pulse on line 16α has a waveform with no notch. In Figure 2, the explanation was made using two divisions, but it is of course possible to have more than two divisions, and the controllability will be even better.

Incidentally, the memory circuit 20 does not output at the same time [Effect] As described above, the motor fast reading control circuit according to the present invention
A case in which the G signal φM is earlier than a predetermined time and then becomes later than the predetermined time is detected, excessive supply power is limited, rotation unevenness or vibration is quickly damped, and stable constant speed rotation is achieved. Furthermore, it is a great advantage that the signal processing flow or logic is simple and it is easy to integrate into 1C.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the morph control circuit according to the present invention, and the second embodiment of the morph control circuit according to the present invention.
The figure shows another embodiment. Figures 3, 4, and 5 are
FIG. 2 is a waveform or time chart of each part of FIG. 2. FIG. 6 shows an example of a conventional motor speed control circuit, and FIG. 7 shows four examples of rotation states. 2.9... Counter 3... Phase detector 10.11.2
0...Memory circuit consisting of D-7 lip 1 flop etc. 4......IJ increaser 5...Motor 9. 18... Coefficient Generator Applicant Epson Corporation Agent Patent Attorney Mogami Tsutomu $ zeφ5 AND/2 -11111''-1,6a' Figure 4φ5 Figure 5

Claims (1)

[Claims] a motor having a frequency generator; a first counter that counts a reference clock to generate a standard clock corresponding to a target speed; a phase detector that detects a phase difference between the signal of the frequency generator and the standard clock; A booster IJ that opens and closes based on a phase difference, in a loop in which the booster energizes the motor, the signal from the frequency generator is reset every time a signal from the frequency generator arrives between the phase detector and the amplifier. a second counter having the same counting container as the first counter; a first storage circuit for storing a carry emitted when the second counter makes a full count; a signal of the frequency generator; A second memory circuit for storing that the interval was shorter than a predetermined time, or a 1g3 memory for separately storing the amount by which the signal interval of the frequency generator attached to the memory circuit of 2 is shorter than the predetermined time. a coefficient generating circuit corresponding to the second memory circuit that generates a circuit in cooperation with the second counter or the reference clock generator, or a coefficient generator corresponding to the third memory circuit group; and an logical product-sum circuit that converts each of the circuits into a predetermined logical product sum. A motor speed control circuit that acts on the phase difference to provide the amplifier.