KR970031307A - Power saving DL devices - Google Patents

Power saving DL devices Download PDF

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Publication number
KR970031307A
KR970031307A KR1019950045517A KR19950045517A KR970031307A KR 970031307 A KR970031307 A KR 970031307A KR 1019950045517 A KR1019950045517 A KR 1019950045517A KR 19950045517 A KR19950045517 A KR 19950045517A KR 970031307 A KR970031307 A KR 970031307A
Authority
KR
South Korea
Prior art keywords
locking
power saving
clock
system clock
phase
Prior art date
Application number
KR1019950045517A
Other languages
Korean (ko)
Other versions
KR0146083B1 (en
Inventor
김대정
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950045517A priority Critical patent/KR0146083B1/en
Publication of KR970031307A publication Critical patent/KR970031307A/en
Application granted granted Critical
Publication of KR0146083B1 publication Critical patent/KR0146083B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Abstract

본 발명은 디엘엘과 이를 제어하는 구변장치에 관한 것으로, 특히 고주파수 및 넓은 주파수범위를 가지는 아날로그 디엘엘에 있어서, 록킹(1ooking)시에 위상 정보를 잃지 않는 범위내에서 최대한의 전류 소모를 억제할 수있는 절전형 디엘엘 장치를 구현하는데 목적이 있는 것으로, 이러한 목적은 외부에서 인가되는 시스템 클럭과 주파수와 같고 일정한 위상관계를 가지는 칩 클럭을 발생하는 디엘엘과, 상기 시스템 클럭을 인가받아 이를 분주하여 제어신호를 생성한 다음 이를 각 단에 인가하는 분주부와, 상기 분주부의 제어신호에 의해 디엘엘의 록킹상태 여부를 판단하여 록킹이 되었다고 판단되면 이의 록킹정보를 저장하는 록킹 검출부와, 상기 록킹 검출부에 의해 록킹정보가 저장되면 상기 디엘엘 및 록킹 검출부로 하여금 절전모드를 수행하게 하는 컨트롤러로 구성함으로써 달성된다.The present invention relates to a DL and a control device for controlling the same. Especially, in an analog DL having a high frequency and a wide frequency range, it is possible to suppress the maximum current consumption within a range in which phase information is not lost during locking. The purpose is to implement a power-saving DL device capable of generating a chip clock having a constant phase relationship with a frequency equal to the frequency of the system clock applied from the outside, and receiving and dividing the system clock by receiving the system clock. A dispensing unit for generating a control signal and applying the same to each stage, a locking detection unit for storing the locking information if it is determined that the locking is performed by determining whether the lock state of the DL is determined by the control signal of the dispensing unit, and the locking unit; When the locking information is stored by the detector, the DL and the locking detector cause the power saving mode to be performed. This is accomplished by configuring a controller to

Description

절전형 디엘엘 장치Power saving DL devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 절전형 디엘엘 장치를 나타낸 도.Figure 2 shows a power saving DL device of the present invention.

Claims (2)

외부에서 인가되는 시스템 클럭과 주파수와 같고 일정한 위상관계를 가지는 칩 클럭을 발생하는 디엘엘과, 상기 시스템 클럭을 인가받아 이를 분주하여 제어신호를 생성한 다음 이를 각 단에 인가하는 분주부와, 상기 분주부의 제어신호에 의해 디엘엘의 록킹상태 여부를 판단하여 록킹이 되었다고 판단되면 이의 록킹정보를 저장하는 록킹 검출부와, 상기 록킹 검출부에 의해 록킹정보가 저장되면 상기 디엘엘 및 록킹 검출부로 하여금 절전모드를 수행하게 하는 컨트롤러로 구성하여 된 것을 특징으로 하는 절전형 디엘엘 장치.A DL that generates a chip clock having a constant phase relationship equal to the frequency of the system clock applied from the outside, a divider which receives the system clock and divides it to generate a control signal, and then applies it to each stage; If it is determined that the locked state of the DL by the control signal of the divider is determined that the locking has been locked, the locking detection unit for storing the locking information, and if the locking information is stored by the locking detection unit the DL and the locking detection unit to save power Power-saving DL device, characterized in that configured as a controller to perform a mode. 제1항에 있어서, 디엘엘은 외부에서 인가되는 시스템 클럭과 자체 칩 클럭의 위상차를 검출하여 그에대한 위상차 신호를 출력함과 아울러 절전모드신호에 의해 절전모드를 수행하는 위상 검출부와, 상기 위상 검출부의 위상차 신호를 입력받아 적분하여 아날로그 신호를 발생함과 아울러 절전모드신호에 의해 절전모드를 수행하는 루프 필터와, 상기 시스템 클럭을 인가받아 상기 루프 필터에서 출력되는 아날로그 전압에 의해 제어하여 원하는 위상의 클럭을 발생하는 위상 간삽부와, 상기 위상 간삽부에서 출력되는 클럭을 입력받아 이를 분배하여 칩내부의 각 단에 공급함과 아울러 절전제어신호에 의해 절전모드를 수행하는 클럭 분배부로 구성하여 된 것을 특징을 하는 절전형 디엘엘 장치.The phase detector of claim 1, wherein the DL detector detects a phase difference between an externally applied system clock and its own chip clock, outputs a phase difference signal thereto, and performs a power saving mode by a power saving mode signal; Integrates a phase difference signal to generate an analog signal, and performs a power saving mode by a power saving mode signal, and a loop filter that receives the system clock and is controlled by an analog voltage output from the loop filter to control a desired phase. It consists of a phase interpolation unit for generating a clock, and a clock distribution unit for receiving the clock output from the phase interpolation unit and distributes it, supplies it to each stage of the chip, and performs a power saving mode by a power saving control signal. Power saving DL device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950045517A 1995-11-30 1995-11-30 Power saving type dll apparatus KR0146083B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950045517A KR0146083B1 (en) 1995-11-30 1995-11-30 Power saving type dll apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950045517A KR0146083B1 (en) 1995-11-30 1995-11-30 Power saving type dll apparatus

Publications (2)

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KR970031307A true KR970031307A (en) 1997-06-26
KR0146083B1 KR0146083B1 (en) 1998-12-01

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Application Number Title Priority Date Filing Date
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501309B1 (en) 1997-11-07 2002-12-31 Fujitsu Limited Semiconductor device having timing stabilization circuit with overflow detection function

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100413758B1 (en) * 2001-03-26 2003-12-31 삼성전자주식회사 Semiconductor memory device including delay locked loop
KR101175244B1 (en) 2010-04-29 2012-08-22 에스케이하이닉스 주식회사 Semiconductor device and opeating method of the same, memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501309B1 (en) 1997-11-07 2002-12-31 Fujitsu Limited Semiconductor device having timing stabilization circuit with overflow detection function

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KR0146083B1 (en) 1998-12-01

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