KR0146083B1 - Power saving type dll apparatus - Google Patents

Abstract

The present invention relates to a DL and a peripheral device for controlling the same. Especially, in an analog DL having a high frequency and a wide frequency range, it is possible to suppress the maximum current consumption within a range in which phase information is not lost during locking. The purpose of the present invention is to realize a power-saving DL device, which is to receive a chip clock having a constant phase relationship with a frequency equal to the frequency of a system clock applied from the outside, and to receive and control the system clock. A dispensing unit which generates a signal and applies it to each stage, and a locking detector which stores the locking information when it is determined that the locking is performed by determining whether the lock state of the DL is determined by the control signal of the dispensing unit, and the locking detecting unit When the locking information is stored by the DL and the locking detection unit to perform the power saving mode It is achieved by configuring the controller.

Description

Power saving DL devices

1 is a block diagram showing a conventional DL (DLL).

Figure 2 shows a power saving DL device of the present invention.

3 is an input / output waveform diagram of each stage of FIG.

4 is a detailed block diagram of DL of FIG.

5 is an internal block diagram of a second diagram locking detection unit;

6 is an input / output waveform diagram of each stage of FIG.

7 is a detailed circuit diagram of the lock comparison unit of FIG.

8 is an internal circuit diagram of the FIG. 2 controller.

* Explanation of symbols for main parts of the drawings

200: dispenser 210: controller

220: locking detection unit 221: clock control unit

222: Rock Comparator 230: DL

231: phase interpolator 232: loop filter

233: clock divider 234: phase detector

The present invention relates to a Delay Locked Loop (DLL) and a peripheral device for controlling the same. In particular, in an analog DL having a high frequency and a wide frequency range, the phase information is not lost during locking. The present invention relates to a power saving DL device capable of suppressing maximum current consumption.

As shown in FIG. 1, the conventional DL detects a phase difference between an externally applied system clock and its own chip clock (ckfb) and outputs a phase difference signal (vpump) corresponding thereto. ), A loop filter 110 that receives an integrated phase difference signal (vpump) of the phase detector 130 and generates an analog signal (pumpout), and receives the system clock and the loop filter 110. The phase interpolation unit 100, which is controlled by an analog voltage (pumpout) output from the phase, and generates a clock (ckdrv) of a desired phase, and receives and distributes the clock (ckdrv) output from the phase interpolation unit 100. It consists of a clock distribution unit 120 to supply to each stage in the chip, it will be described in detail.

The clock distributor 120 generates a chip clock for driving each stage of the chip, and one of the clocks ckfb is fed back to the phase detector 130 and the phase detector 130. ) Compares the phase of the feedback clock (ckfb) and the system clock (system clock) applied from the outside to apply a digital signal (vpump) of logic high or logic low to the loop filter (110).

Then, the loop filter 110 integrates it, generates an analog signal (pumpout) corresponding thereto, and applies it to the phase interpolator 100, and the phase interpolator 100 is applied from the loop filter 110. By controlling the phase of a system clock applied externally by the size of the analog signal (pumpout), a clock ckdrv having a desired phase is applied to the clock distribution unit 120 serving as a clock buffer.

The clock distributor 120 distributes an input clock (ckdrv) and supplies a chip clock to each end of the chip. When the chip clock is locked at a desired phase, the phase detector 130 The phase difference signal (vpump) output from the oscillation is repeated while the logic high and low are repeated. In this process, the system clock and the chip clock applied to the inside of the chip are applied. By locking, the frequency and phase relationship are matched.

However, since the analog DL consumes a large amount of current in a stand-by state in a locked state, this has a problem of acting as a big disadvantage when integrated in the chip.

Accordingly, the present invention has the object of minimizing power consumption by storing the locking information and turning off the circuit generating the locking when the DL becomes locked in view of such a problem. It explains in detail.

As shown in FIG. 2, the power-saving DL device of the present invention includes a DL 230 that generates a chip clock having a constant phase relationship with a frequency equal to the frequency of the system clock applied from the outside. In response to the system clock being applied, the system clock divides it to generate a control signal ClkRef, lockEvalWin, qn, and then applies it to each stage, and a control signal of the division part 200 The lock detector 220 stores the lock information by determining whether the lock is in the locked state by the lockEvalWin, and when the lock information is stored by the lock detector 220, the lock detector 220 stores the lock information. 230 and the controller 210 for causing the locking detection unit 220 to perform a power saving mode.

Meanwhile, as illustrated in FIG. 4, the DL 230 detects a phase difference between an externally applied system clock and its own chip clock ckfb and outputs a phase difference signal (vpump) corresponding thereto. In addition, the phase detection unit 234 performing the power saving mode by the power saving mode signal PwrSave and the phase difference signal vpump of the phase detection unit 234 are integrated to generate an analog signal (pumpout). The loop filter 232 which performs the power saving mode by the mode signal PwrSave and the system clock are applied and controlled by the analog voltage (phaseinfo) output from the loop filter 232 to control the desired phase. A phase interpolation unit 231 generating a clock clock ckdrv and a clock ckdrv output from the phase interpolation unit 231 are received and distributed to each stage of the chip and a power saving mode signal PwrSave. Sleep mode by) Constitute a clock distributor 232 to perform.

The operation and effects of the present invention configured as described above will be described in detail with reference to FIGS. 2 to 8.

The DL 230 generates a chip clock having the same phase relationship with the system clock applied from the outside and having a constant phase relationship, and applies it to each stage inside the chip, and the system clock And outputs a digital signal (vpump) of the phase difference between the chip clock and the chip clock.

On the other hand, the division unit 200 receives the system clock (system clock) and divides it, the reference clock (ClkRef) and the reference clock as a signal for determining the locking state as shown in Figure 3 (c) The lock determination signal lockEvalWin having three cycles of ClkRef and the power saving mode execution signal q _N for determining the duration of the power saving mode are output.

The locking detector 220 receives the reference clock ClkRef, the locking determination signal lockEvalWin, and the phase difference signal vpump output from the DL 230, and receives a logic high of the locking determination signal lockEvalWin. When the frequency of the phase difference signal vpump and the reference clock ClkRef output from the DL 230 is measured in time, and the number of transitions of the phase difference signal vpump is larger than the reference clock ClkRef, It is determined that the device is in the locked state, and outputs the power saving mode drive signal pwrSaveIn as shown in FIG. 3 (a) to logic high and stores the locking information.

Then, when the power saving mode driving signal pwrSaveIn output from the locking detection unit 220 is logic high, the controller 210 receives a power saving mode performing signal q _N output from the division unit 200 for one period. During operation, the power saving mode signal pwrSave is maintained at a logic high to output the DL 230 and the locking detection unit 220 that consume a lot of power to perform the power saving mode.

On the other hand, the power saving mode release signal (mode exit) for releasing the power saving mode as shown in FIG. 3 (b) applied to the controller 210 maintains a logic high while in the power saving mode and then exits the power saving mode. If it is to be released, it becomes a logic low signal, thereby making the power save mode signal pwrSave a logic low, thereby releasing the DL 230 and the locking detector 220 from the power save mode.

At this time, the power saving mode driving signal (pwrSaveIn) output from the locking detection unit 220 also outputs a logic low to maintain the power saving mode release state.

FIG. 4 is a detailed block diagram of the DL 230. The operation process is the same as in the related art, but in the present invention, the power saving mode signal pwrSave output from the controller 210 is stored in the loop filter 232 and the output distribution unit. 233 and, when applied to the phase detection unit 234, the logic is turned off to remain in the power saving mode. If the logic is kept to be low, the power saving mode is released to operate normally.

5 is an internal block diagram of the locking detection unit 220. The clock control unit 221 is a locking determination signal (lockEvalWin) output from the division unit 200 as shown in FIG. 6 (a) or (b). ), The reference clock ClkRef, and the phase difference signal vpump output from the phase detection unit 234 of the DL 230 are received, and the locking determination signal (D) as shown in FIG. In the logic high section of lockEvalWin, the falling edges of the reference clock ClkRef and the phase difference signal vpump are detected to generate pulses vi and vq, and the locking state determination signal eq as shown in (f) and A control signal eval for controlling the lock comparator 222 is output.

Then, in the lock comparator 222 as shown in FIG. 7, the capacitors C1 and C2 retain the charge of the clocks vi and vq converted to current by the transistors P1 and P2, and control signals. While (eval) is logic high, the input voltage of the sense amplifier (sa) is provided, and if the number of clocks (vq) is greater than the clock (vi), the lock state is recognized and the power saving mode drive signal (pwrSaveIn) is set to logic high. do.

In this case, the capacitors C1 and C2 are discharged in a section in which the control signal eval and the clock eq are both logic high.

8 is an internal circuit diagram of the controller 210. The power saving mode driving signal pwrSaveIn is kept at logic high in the power saving mode, and if the power saving mode is to be released, the mode exit signal logic is output. By changing low, the power saving mode signal (pwrSave) is set to logic low to cancel the power saving mode.

As described above, the present invention detects when the DL is in a locked state and stores the locking information, and then turns off the circuit generating the lock to minimize the power consumption, thereby minimizing power consumption. The power saving effect becomes.

Claims (2)

A DL that generates a chip clock having a constant phase relationship equal to the frequency of the system clock applied from the outside, a divider which receives the system clock and divides it to generate a control signal, and then applies it to each stage; If it is determined that the locking state is determined by the control signal of the dispenser, the lock detection unit stores the locking information thereof, and when the locking information is stored by the locking detection unit, the DL and the lock detection unit Power-saving DL device, characterized in that configured as a controller to perform a mode. The phase detector of claim 1, wherein the DL detector detects a phase difference between an externally applied system clock and its own chip clock, outputs a phase difference signal thereto, and performs a power saving mode by a power saving mode signal; Integrates a phase difference signal to generate an analog signal, and performs a power saving mode by a power saving mode signal, and a loop filter that receives the system clock and is controlled by an analog voltage output from the loop filter to control a desired phase. And a clock divider for generating a clock, and a clock divider for receiving the clock output from the phase interpolator and distributing the same, supplying the clock to each stage of the chip, and performing a power saving mode by a power saving control signal. Power saving DL device.