JPH0244557A - Capstan servo device - Google Patents

Abstract

PURPOSE:To prevent the limitation of a gear from being received by executing the integer number-dividing or non-integer number-dividing of a capstan FG signal, defining an output as a comparing signal, detecting a phase error signal with phase comparison to a reference signal and controlling the phase error signal. CONSTITUTION:An FG signal S1 to be obtained from a capstan (F2) 2 by the rotation of a capstan motor 1 is inputted to a dividing means 4 and a speed comparing means 6. In the means 4, the frequency of the signal S1 is divided by an integer or a noninteger so as to obtain a frequency which is equal to the frequency of a reference signal S2, and a PG signal S3 is prepared. The signal S3 is inputted to a phase comparing means 5 together with the signal S2 and the phase comparison is executed. Then, a phase error signal S4 is detected. On the other hand, the means 6 detects a speed error signal S5 by executing frequency discrimination for the signal S1. Then, the signals S4 and S5 are mixed by a mixing means 7 and a mixed output S6 is obtained. The rotating speed and phase of a motor 1 are controlled by this output S6. Thus, a servo device can be realized not to receive the limitation for the shaft diameter and tooth number of the gear at all.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a capstan servo device, and it is possible to perform FG multiplied signal phase comparison by using frequency dividing means capable of integer frequency division or non-integer frequency division of a capstan FG signal. To provide a capstan servo device that can obtain a divided output of the same frequency as a reference signal and compare the phases even when the frequency cannot be obtained at an integral multiple of the frequency of the reference signal.

In the conventional capstan servo device of a magnetic recording/reproducing device, in order to realize phase servo during recording, the output of a frequency generator (hereinafter referred to as FG) that detects the rotational speed of the capstan motor (hereinafter referred to as FG multiplied signal) is used to realize phase servo during recording. ) is divided by frequency dividing means and used. This frequency divided output is commonly called a PG multiplied signal. In the capstan servo device, this PG double signal is used as a comparison signal for phase servo, and the capstan servo is implemented by comparing the phase with a reference signal (for example, a vertical frame synchronization signal of 30 Hz). This is a conventionally known technique and need not be explained.

Problems to be Solved by the Invention However, in the above configuration, the frequency dividing means can only perform integer frequency division, so in order to obtain a PG multiplied signal with the same frequency as the reference signal, the FG multiplied signal must be an integer multiplied by the reference signal. There was a problem in that it was necessary to select the

Generally, the tape speed Vt when a magnetic tape is directly driven by a capstan motor is calculated by the following equation (1).

Vt=π・D-N-FPG/Z
(1) However, π is pi, D is the diameter of the capstan shaft, N is the frequency division ratio, FPG is the PG multiplied signal frequency, and Z is the number of teeth of the FG. Note that N·F'PG is FG times the signal frequency FFG.

In equation (1), vt takes a specific value based on the tape format of the magnetic recording/reproducing device. Also, since the PG multiplied signal is specified, D is adjusted so that the value obtained by dividing the product of D and N by Z is constant as shown in equation (2).

N and Z must be selected.

D@N/Z = constant (2) Normally, it is more economical to use a standard product for the capstan shaft, but
Since N and Z are limited to integers, special products must be used in some cases. If you are lucky enough to use a standard product, there will be no problem, but if that is not the case and you cannot use anything other than a standard product, you will have to set the PG double signal frequency FPC to a frequency different from 30H2. In this case, the vertical frame synchronization signal cannot be used as a reference signal. Therefore, there was no choice but to generate and use an internal reference signal using a reference signal generator.

As is clear from the above explanation, in the conventional capstan servo device, the frequency dividing means was capable of only integer frequency division, and therefore there were many restrictions in the design of the device.

The present invention solves the above-mentioned problems, and provides a capstan servo device equipped with frequency dividing means that can obtain a PG multiplied signal of a desired frequency from an FG multiplied signal without any design restrictions. The purpose is to

Means for Solving the Problems To achieve this object, the capstan servo device of the present invention includes frequency dividing means for dividing a capstan FG signal by an integer frequency or a non-integer frequency, and comparing the output of the frequency dividing means. and a phase comparison means for detecting a phase error signal by phase comparison with a base signal as a signal, the capstan motor is controlled by the phase error signal, and the frequency dividing means varies the capstan FG signal. a variable frequency dividing means for frequency division; a calculating means for calculating in synchronization with the output of the variable frequency dividing means; and a correcting means for correcting the timing of the output of the variable frequency dividing means in accordance with the output of the calculating means; and switching means for switching the frequency division ratio of the variable frequency division means in accordance with the output of the calculation means, and the output of the correction means is configured to be a frequency division output.

In addition to the above-described configuration, the present invention also includes speed comparison means for frequency-discriminating the capstan FG signal to detect a speed error signal, and mixing means for mixing the speed error signal and the phase error signal, It has a configuration in which the capstan motor is controlled by the output of the mixing means.

Effect The present invention has the above-described configuration, in which the switching means switches the frequency division ratio of the variable frequency dividing means according to the calculation output obtained by the calculation means, and the correction means is controlled by the calculation output to perform variable division. Since the timing of the output of the frequency means can be corrected, integer frequency division or non-integer frequency division is possible, and the capstan FG signal can be frequency divided to a desired frequency. However, by using the output obtained from the correction means as the divided output of the frequency dividing means, it is possible to realize a capstan servo device with no design restrictions.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a capstan servo device in an embodiment of the present invention. In Figure 1, 1
2 is a capstan motor, and 2 is an FGl that detects the rotation speed of capstan motor 1 and obtains a capstan FG signal Sl.
3 is an input terminal into which the reference signal S2 is input; 4 is a frequency dividing means for dividing the FG signal Sl by an integer or a non-integer; and 5 is a comparison between the reference signal S2 and the PG signal S3 which is the output of the frequency dividing means 4. Phase comparison means for comparing the phases as signals and detecting a phase error signal S4; 6 a speed comparison means for frequency-discriminating the FG signal S+ and detecting a speed error signal S5; 7 mixing the phase error signal S4 and the speed error signal S5. is a mixing means,
The capstan motor 1 is controlled by the output S6 of the mixing means 7. Further, 8 to 11 are internal configuration means of the frequency dividing means 4, 8 is a variable frequency dividing means that variably divides the frequency of the FG signal Sl, and 9 is a calculation operation in synchronization with the variable frequency dividing output S7 of the variable frequency dividing means 8. IO is a correction means for correcting the timing of the variable frequency division output S7 of the variable frequency division means 8 according to the calculation output S8 of the calculation means 9; IO is a correction means for correcting the timing of the variable frequency division output S7 of the variable frequency division means 8; This is a switching means for creating a frequency division ratio of the variable frequency division means 8 and obtaining the frequency division output of the frequency division means 4, ie, the PG signal S3, from the correction means 1O.

The operation of the capstan servo device of this embodiment configured as described above will be described below.

The FG signal St obtained from the FG 2 by the rotation of the capstan motor 1 is input to the frequency dividing means 4 and the speed comparing means 6. The frequency dividing means 4 divides the FG signal St by an integer or a non-integer so that it becomes equal to the frequency of the reference signal S2,
A frequency divided output, that is, a PG signal S3 is created. This PG signal S3 is input to the phase comparison means 5 together with the reference signal S2, and the phases are compared to detect a phase error signal S4. on the other hand,
The speed comparison means 6 detects the speed error signal S5 by frequency-discriminating the FG signal Sl. The phase error signal S4 and the speed error signal S5 are mixed in the mixing means 7 to obtain a mixed output S6. The rotation speed and phase of the capstan motor 1 are controlled by this mixed output S6. In addition,
The speed comparison means 6 is necessary when a DC motor is used as the capstan motor 1, but is not necessary when a motor that does not require speed control, such as a synchronous motor, is used. In this case, the mixing means 7 is also unnecessary, and the capstan motor 1 can be directly controlled by the phase error output S4.

The above is an explanation of the operation of the capstan servo device, and the present invention is particularly characterized by the frequency dividing means 4. The operation of the frequency dividing means 4 will be explained below.

The variable frequency dividing means 8 variably divides the frequency of the FG signal Sl.

The variable frequency division output S7 of the variable frequency division means 8 is input to the calculation means 9 and the correction means IO. The calculation means 9 performs necessary calculations in synchronization with the variable frequency division output S7, and creates a calculation output S8. The correction means 10 outputs a variable frequency division output S according to the calculation output S8.
Correct the timing of step 7. Switching means! ■ is the calculation output S
A switching signal S9 is created in accordance with 8, and the frequency division ratio of the variable frequency dividing means 8 is switched. Then, the PG signal S3, which is the frequency-divided output of the frequency dividing means 4, is obtained from the correction means IO.

Here, if the frequency division by the variable frequency dividing means 8 is sufficient to be an integer frequency division, the calculation means 9 does not perform the calculation, and the switching means 11 does not switch the frequency division ratio.

Needless to say, in this case, means 9 to ti are unnecessary. That is, the frequency dividing means 4 fully exhibits its characteristics when performing integer frequency division, and can also perform integer frequency division. Thereby, the frequency dividing means 4 capable of integer frequency division and non-integer frequency division can be realized.

FIG. 2 is a waveform diagram showing an example of the operation of the frequency dividing means 4 in the present invention. Here, the variable frequency dividing means 8 shows an example in which an up counter is used as a frequency dividing counter, and the PG signal S3 shows an example in which the period is 3.7 times that of the FG times signal l. Further, the correction means 10 adjusts the fineness of the correction to 1/1 of the period of the FG multiplied signal l.
An example is shown in which the value is set to 10. Therefore, the correcting means 10 only needs to correct the timing using a clock having a frequency ten times the frequency of the FG multiplied signal, and this can be easily realized using a digital delay circuit.

Note that the period ratio of 3.7 between the PG signal S3 and the FG multiplied signal t is 37 when converted to the number of clock pulses. Also,
An example is shown in which a down counter that can repeatedly count from 9 to 0 is used as the calculation means, and 3 is subtracted in synchronization with the variable frequency division output S7. This subtraction value is a value obtained by subtracting 37 from 40, and is a difference with respect to the period of an integral multiple of the FG signal. Here, if an up counter that repeatedly counts from 0 to 9 is used, the difference value 7 obtained by subtracting 30 from 37 may be added. The calculation speed of the calculation means 9 only needs to be completed immediately before the correction means IO requires the correction value. Further, the illustrated time tQ-t12 is a period that is 3.7 times the period of the FG times signal t, that is, the period of the PG times signal.

In FIG. 2, waveform A is the FG multiplied signal t, waveform B is the frequency dividing operation of the variable frequency dividing means 8, and waveforms CN and CI are the outputs (variable The waveform E corresponds to the operation of the calculation means 9, that is, the operation of subtracting 3, and the waveform E corresponds to the operation of the switching means 11.
Output obtained by comparing the calculated output S8 with a predetermined value (3 in this case) (“H” if the predetermined value or more, “L” if there is no groove)
The waveform F is the output obtained by latching this comparison output at the falling edge of the variable frequency division output S7N, that is, the switching signal S9. Corrected output (
The width of the pulse indicates the amount of correction), and the waveform H shows the pulse created by the falling edge of this correction output, that is, the PG signal S3.

Now, the period of PG signal S3 is 3.7 of the period of FG signal S+.
Since it is a double, there is a difference of -0, 3, and +0.7 compared to the integer frequency division value of 4.3 before and after that. This is -3, +7 when converted into the number of clock pulses.

Therefore, if the frequency is simply divided by an integer, a high frequency division output lower than the frequency of the PG signal S3 will be obtained, and the timing will be delayed in phase and shifted further and further in the direction of advance.In the end, the frequency division of the PG multiplied signal with the same frequency will be obtained. I can't get any output.

Therefore, the present invention provides a switching signal S9(
The frequency division ratio is switched between 3 and 4 (divided by 3 when low, divided by 4 when high) using waveform F), and a variable frequency divided output S7N (waveform CN) is obtained earlier than each time from tO to t12. By correcting this using the calculation output S8 (waveform D) in the correction means 10, an output signal S3 (waveform H) having the same timing as 10-112 is obtained.

For convenience of explanation, time 10 is the FG multiplied signal t (waveform A).
This will be explained by assuming that it coincides with the rise of . Actually, it doesn't matter what time it starts, it is the calculation output S
8. Time t.

The calculation output S8 is O. The calculating means 9 shows the case of subtraction (waveform D). The correction means IO has a correction fineness of 1
Since it is set to 71O, it is only necessary to perform ten different corrections. Therefore, the calculation means 9 only needs to be able to output ten different values from 9 to O, which correspond to the subtraction shown in the waveform.

As can be seen from the waveform diagram, tO~tl, t3~t4. tG
~t7. Between tlO and tll, the frequency is divided by 3, and tl-t
2. t2-t3. t4-t5. t5~tG.

t7-t8. t8-t9. t9-t10. t
If the frequency is divided by 4 between 11-t12, each time t
Variable frequency division output S7N (m type C
M) can be obtained.

At this time, the difference between the rising edge of the variable frequency division output S7N and each time is 0.0 from 10 to t12. 7.4.1.8
．． 5.2.9.6.3.0.7.4. Therefore, by using this value as a correction value, it is possible to obtain the PG signal S3 at the desired timing.

The waveform G shows the correction amount, and each correction amount is a value obtained by subtracting 3 from the previous value. This corresponds to the above-mentioned difference -3. The value obtained by this calculation is the calculation output S8 shown in the waveform. Here, the calculation by the calculation means may be performed after each time and before the next correction starts.

For rotation, use the variable frequency division output S71 shown in the waveform diagram CI,
Calculations are performed in synchronization with the falling edge of this signal.

The frequency dividing ratio in the variable frequency dividing means 8 may be switched by dividing the frequency by 4 when the previous calculation output S8 is 3 or more, and by dividing by 3 when the previous calculation output S8 is 3 or more. This is done by comparing the calculated output S8 with a predetermined value (3 in this case) in the switching means 11 to obtain an output, and latching this magnitude comparison output at the falling edge of the variable frequency division output S7N to create the switching signal S9. , it is sufficient to switch using this switching signal S9.

In rotation, when the switching signal S3 shown in waveform F is low, the frequency division ratio N=3, and when it is high, the frequency division ratio is N=4. Here, the predetermined value used for the magnitude comparison corresponds to the above-mentioned difference -3.

This means that if the previous correction value is less than 3, the next correction value will be 7 or more, that is, the next frequency division ratio will be smaller.

As described above, the calculation means 9 performs calculations in synchronization with the variable frequency division output S7 of the variable frequency division means 8, and the frequency division ratio in the variable frequency division means 8 is switched according to the calculation output S8, and the correction means The correction means I performs timing correction in IO.
A PG signal S3 of a desired frequency can be obtained from O. This signal S3 is the frequency divided output of the frequency dividing means 4.

In addition, in the above explanation, the variable frequency division output S of the variable frequency division means 8
7N rise timing is corrected and variable frequency division output S
Although the case where calculation is performed in synchronization with the rising edge of signal 71 has been described, the present invention is not limited to this. Further, when the calculation means 9 is configured in hardware, it is sufficient to configure a subtracter using a down counter, and when configured in software, it is possible to execute a subtraction program with a microcomputer.

The above is an explanation of the operational example of the frequency dividing means 4 in the present invention using numerical values, but a more general explanation is as follows: (1) First, the frequency fPG of the PG signal S3 is
Frequency of G doubler Sl f FG magnification f FG/ f PG
seek. This is 3.7 times the above value.

(2) Find an integer value Nl when f+a/fpa is rounded up and an integer value N2 when rounded down.

This is the frequency division ratio in the variable frequency division means 8, and if it corresponds to the above value, N1=4. N2=3 (N1=N2+1
).

(3) N1. The difference obtained by subtracting f FG/ f PG from N2 is the multiplication factor f CK/ of the clock frequency fCK used in the correction means 10 for the frequency fFG of the FG doubler Sl.
Multiply by fFG to find the difference M-1M' converted into the number of clock pulses. M-= (f FG/ f PG
-N I)・f CK/ f FG.

M″″= (f FG/ f PG-N2) ・f
CK/f FG, and if it corresponds to the above value, M
-=-3, M''=+7, which are the subtraction value and addition value in the calculation means 9.

The frequency dividing means 4, which constitutes the main part of the present invention, has been explained above, but the present invention uses such a frequency dividing means so that the capstan FG signal St is an integral multiple of the frequency of the reference signal S2 for phase comparison. Even if this is not possible, a PG signal S3 having the same frequency as the reference signal S2 can be obtained. This results in
It is possible to realize a capstan servo device in which the shaft diameter of the capstan and the number of teeth Z of the FG can be arbitrarily selected.

In addition, the phase comparison means 5 and the speed comparison means 6 in FIG.
, mixing means 7, calculation means 9, correction means 101 switching means I
It goes without saying that f can be realized by program processing (software processing) by a microcomputer.

Effects of the Invention As described above, the present invention makes it possible to arbitrarily select the shaft diameter of the capstan and the number of teeth Z of the FG, which was previously impossible, by using a frequency dividing means capable of integer frequency division or non-integer frequency division. Therefore, it is possible to realize a capstan servo device that is not restricted by the shaft diameter and the number of teeth Z, and the practical effects thereof are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a capstan servo device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing an example of the operation of frequency dividing means, which is a main part of the present invention. 4009 Frequency division means, 5110 Phase comparison means, 6
．． . , speed comparison means, 713. mixing means, 803.
variable frequency dividing means; 9. ,, calculation means, 10. ,,
Correction means, 11,...Switching means. Name of agent: Patent attorney Shigetaka Awano and 1 other person 1-'e
Yahoo "Sudan F-9 -Fcr

Claims (4)

[Claims] (1) Frequency dividing means that divides the capstan FG signal by integer or non-integer frequency, and phase comparison means that detects a phase error signal by phase comparison with a reference signal using the output of the frequency dividing means as a comparison signal. The capstan motor is controlled by the phase error signal, and the frequency dividing means includes variable frequency dividing means for variably frequency dividing the capstan FG signal, and calculation in synchronization with the output of the variable frequency dividing means. a calculation means for correcting the timing of the output of the variable frequency division means according to the output of the calculation means; and a switching means for switching the division ratio of the variable frequency division means according to the output of the calculation means. A capstan servo device, characterized in that the output of the correction means is a frequency-divided output. (2) The capstan servo device according to claim 1, wherein the phase comparison means, calculation means, correction means, and switching means are constructed using a microcomputer. (3) A speed comparison means for frequency-discriminating the capstan FG signal to detect a speed error signal, a frequency division means for dividing the capstan FG signal by an integer or a non-integer, and a signal for comparing the output of the frequency division means. and a mixing means for mixing the speed error signal and the phase error signal, the capstan motor being controlled by the output of the mixing means. The frequency dividing means has a configuration in which the capstan F
variable frequency dividing means for variably frequency-dividing the G signal; calculating means for calculating in synchronization with the output of the variable frequency dividing means; and correcting the timing of the output of the variable frequency dividing means in accordance with the output of the calculating means. A capstan servo device comprising a correction means and a switching means for switching the frequency division ratio of the variable frequency division means according to the output of the calculation means, and the output of the correction means is a frequency division output. . (4) The capstan servo device according to claim 3, wherein the phase comparison means, speed comparison means, mixing means, calculation means, correction means, and switching means are constructed using a microcomputer.