JPH06296373A - Inverter apparatus using pwm control - Google Patents

Abstract

PURPOSE:To provide an inverter using PWM control which can reserve the minimum pulse width without delayed reponse of the control system and lowered voltage utilization factor. CONSTITUTION:A change-over timing generator 3 generates a timing pulse INT1 at the timing where the carrier Cao becomes 1/2 of the maximum and minimum values and a change-over timing delay circuit 4 generates a timing pulse INT2 which is delayed as much as the time which is obtained by subtracting the minimum pulse width from the timing where the timing pulse INT1 is generated. A change-over timing selecting part 5 selects any one of the timing pulses INT1, INT2 in accordance with the reference voltage Vrl output from a controller 1. A PWM circuit 6 loads the reference voltage Vrl in this timing to its comparator and outputs the PWM signal GP in accordance with a triangular wave carrier Ca2 output from a carrier phase shift circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device using PWM control, and more particularly to an inverter device using PWM control for ensuring a gate signal having a minimum pulse width.

[0002]

2. Description of the Related Art When an electric motor is driven by an inverter using PWM (Pulse Width Modulation) control, it may be controlled by a sample value control system using a microprocessor. At this time, a gate pulse for PWM control may be output depending on the comparison between the voltage reference, which is the control output, and the carrier. FIG. 7 shows the relationship between the conventional voltage reference and the carrier in such a case. FIG. 7 shows an example in which the gate signal is output in a period in which the voltage reference is larger than the carrier. As shown in FIG. 8, the main circuit of the PWM inverter has a switching element bridge-connected between the positive and negative sides of the DC voltage source, and the switching elements on the positive side and the negative side operate complementarily (complementary). 7's
A gate signal that is the reverse (inverted) of the gate signal is also output. Also,
Updating of the voltage reference in the sampled-data control system is performed by the return point P ₁ to P ₇ of the carrier triangular wave, voltage reference magnitude minimum pulse width less the width of the gate is usually limited to ± V _L1 - DOO signal Is not output. However, as a result of the sample calculation, the voltage reference is the maximum voltage of the carrier ± V
When the voltage exceeds _max , the voltage reference may be fixed to ± V _max and the ON state or the OFF state of the switch element may be maintained. Section of P ₄ to P ₆ in FIG. 7 shows this state. In this case, a pulse having a width half the minimum pulse width may be output at points P ₄ and P ₆ .

Driving the switching element with such a narrow pulse causes damage to the switching element and must be avoided. In order to prevent the generation of this narrow pulse, the magnitude of the voltage reference is limited to ± V _{L2 so} that a gate signal that is normally twice the minimum pulse width or less is not output, and P ₄ , P There is a method to secure the minimum pulse width at the time of ₆ .

As another method, as shown in FIG. 9, the voltage-based limit value remains ± V _L1 and the narrow pulse less than the minimum pulse width is removed after the PWM circuit 6, or the minimum pulse width is removed. There is a method in which a pulse correction unit 101 for fixing the pulse width is provided, and the excess or deficiency of the output voltage is adjusted by subsequent control by feeding back the correction amount to the controller 1.

[0005]

In the above-mentioned conventional method, there is a problem that the voltage utilization factor decreases in the former case and the response of the control system slows in the latter case. The present invention has been made to solve the above problems, and an object of the present invention is to provide a narrow pulse having a minimum pulse width or less without slowing the response of the control system and further reducing the voltage utilization rate. Inverter using PWM control without output
To provide a data processing device.

[0006]

In order to achieve the above object, the present invention has the following constitution. (1) A controller that updates a voltage reference with a half cycle of the pulse width modulation cycle as a control cycle, and a gate that is pulse width modulated by comparing the triangular wave carrier having the pulse width modulation cycle with the voltage reference. In an inverter device provided with a comparator for generating a signal, timing generation means for comparing the carrier with upper and lower threshold values and defining timing points of a leading edge and a trailing edge of a predetermined minimum pulse width. When,
Timing selecting means is provided for setting the update timing of the voltage reference input to the comparator according to the value of the voltage reference for each control cycle to either the timing point of the leading edge or the trailing edge.

(2) An inverter provided with a controller for updating a voltage reference with a half cycle of the pulse width modulation cycle as a control cycle, and a means for outputting a gate signal whose pulse width is modulated according to the voltage reference. Pulse generator for generating a first timing pulse for each control cycle, and for generating a second timing pulse delayed by a time obtained by subtracting a predetermined minimum pulse width from the control cycle Means, timing selecting means for selecting one of the first and second timing pulses according to the value of the voltage reference for each control cycle, and a predetermined value according to the voltage reference by the selected timing pulse. Preset, alternate addition / subtraction mode for each control cycle
An up / down counter that counts clock pulses of a constant cycle by a mode and outputs a gate signal of a predetermined logical value when the count value exceeds a predetermined count value; the addition and subtraction modes and the timing selection means. There is provided a preset value determining means for correcting the preset value of the up / down counter according to which timing pulse is selected.

[0008]

[Action]

(1) In the configuration of (1) above, the timing of updating the voltage reference input to the comparator is normally performed at the timing of the trailing edge. However, when the voltage reference of the previous control cycle exceeds the upper and lower limit threshold range and the voltage reference of the current control cycle falls within the upper and lower limit threshold range, it is input to the comparator. The voltage reference is updated at the timing of the leading edge. As a result, a narrow pulse having a width equal to or smaller than the minimum pulse width is not output. (2) In the configuration of (2), when the first timing pulse is selected and the up / down counter performs addition, the preset value determination means sets V _r1 + V _min as a preset value and the up / down counter subtracts. When the second timing pulse is selected when V _r1 + V _max −V _min is set as a preset value and the up / down counter performs addition, V _r1 −V _min is set as the preset value and the up / down counter performs subtraction. When _doing , V _r1 +
Let V _max + V _min be the preset value. However, V _r1 is a voltage reference, V _min is a value determined by the minimum pulse width, and V _max is a voltage reference maximum value. As a result, a narrow pulse having a width equal to or smaller than the minimum pulse width is not output.

[0009]

FIG. 1 shows a first embodiment of the present invention. In FIG. 1, a controller 1 has a speed control function for comparing a speed reference and a speed feedback and outputting a current reference, and a current control for comparing a current reference and a current feedback and outputting a voltage reference V _r1. It has a function. The carrier generation circuit 2 includes a counter, counts a clock having a constant frequency, and generates a sawtooth carrier C _a0 having a period T ₀ as shown in FIG. 2, which is defined as a modulation frequency for PWM control. When the switching timing generator 3 recognizes the maximum value N _max of the carrier C _a0 or a value ½ of the maximum value N _max , it generates the timing pulse INT ₁ . This timing pulse INT ₁ is used as an interrupt signal of the controller 1, and this cycle (T _0/2 ) becomes the control cycle. The switching timing delay circuit 4 includes a timer,
From the time when the timing pulse INT ₁ is generated, T _0/2
Generates a timing pulse INT ₂ delayed by −T _min (a time obtained by subtracting the minimum pulse width from the control cycle). These timing pulses INT ₁ and INT ₂ are used as voltage reference switching timing signals which will be described later.

The switching timing selection unit 5 is a controller.
The timing pulse INT ₁ or INT ₂ is selected according to the voltage reference V _r1 output from the laser ₁
Input to the WM circuit 6. In this case, voltage reference output in the previous control cycle, and beyond the threshold range as determined by the constraints of the minimum pulse width of the element (the range of ± V _L1 in FIG. 2), in the current control cycle Timing pulse INT ₂ is selected when the voltage reference to be output falls within the above threshold range, and timing pulse INT ₁ is selected in all other cases.
Select.

The voltage reference V _r1 is output for each phase and the above-mentioned determination is performed for each phase.
When T ₂ is selected, the timing pulse of all phases is IN
Select T ₂ to suppress the generation of current ripples due to timing pulse switching. The PWM circuit 6 has a comparator, and the voltage reference V _r1 is loaded as one input of the comparator at any timing of the timing pulses INT ₁ and INT ₂ selected by the switching timing selecting section 5. . The triangular wave-shaped carrier C _a2 output from the carrier phase shift circuit 7 is input to the other input of the comparator, and PWM-controlled gate signal G _P is output according to the magnitude relationship. The carrier phase shift circuit 7 obtains a sawtooth wave signal obtained by shifting (advancing phase) the carrier C _a0 by a predetermined phase (a phase corresponding to the time of T _min / 2), and at the 0 point and the N _max / 2 point. By inverting the polarity of the rate of change, the triangular wave carrier C _a2 shown in FIG. 2 is output.

In the above configuration, when the voltage reference V _r1 as shown in FIG. 3 is output, the switching timing selecting section 5 selects the timing pulse INT ₁ in each control cycle of the control cycles T _{1 to} T ₄ , and INT. _At the timing of ₁ , the voltage reference V _r1 is loaded into the comparator of the PWM circuit 6. However, in the control cycle T ₅ , the voltage reference V _r1 output this time returns to within the range of ± V _L1 , so the switching timing selection unit 5 selects the timing pulse INT ₂ and INT ₂
At this timing, the voltage reference V _r1 is loaded into the comparator. In the control cycle T ₆ , again, the timing pulse IN
T ₁ is selected. Therefore, the gate signal G _P is assured of the minimum pulse width T _{min in} both the control period T ₃ and the control period T ₅ .

According to the present embodiment, the switching timing selecting section 5 selects an appropriate switching timing that does not output a narrow pulse having a width equal to or smaller than the minimum pulse width for any voltage reference, without delaying the response of the control system. Moreover, it is possible to output a voltage reference above the threshold value range without lowering the voltage utilization rate.

The section for outputting the voltage reference above the threshold range is fixed at V _{max and} has a width of 60 ° per phase. Further, since the voltage reference can output up to 1.15 times the limit voltage reference, the present invention enables the expansion of the voltage use range of 1.15 · V _min compared to the conventional method.

FIG. 4 shows an essential part of the second embodiment of the present invention.
In FIG. 4, the clock generator 21 generates a clock pulse having a constant cycle. The switching timing generator 22 divides the frequency of the clock pulse, and as shown in FIG. 5, the timing pulse INT having a period of 1/2 of the pulse width modulation period T _{0.
Raises 1} . The controller 1, the switching timing delay circuit 4, and the switching timing selector 5 are the same as those in FIG. The voltage reference conversion unit 23 is controlled according to commands from the PWM circuit 24 and the switching timing selection unit 5.
Voltage reference V _r1 corrected voltage reference V _r1
Output _r2 . The PWM circuit 24 includes an up / down counter, and the value of the voltage reference V _r2 is preset at any timing of the timing pulses INT ₁ and INT ₂ , and the clock pulse is alternately added and subtracted for each control cycle, and the count value is predetermined. A gate signal G _P of "1" or "0" is output depending on whether the value is greater than or less than the value.

In the above structure, when the voltage reference V _r1 is output as shown in FIG. 5, the voltage reference V corrected by the up / down counter of the PWM circuit 24 by the timing pulse INT _{1 in the} control cycles T _{1 to} T _{4. It} is preset to the value of _r2 and repeats addition and subtraction. In this case, the voltage reference converter 23 corrects V _r2 = V _r1 + V _min (1) when adding, and corrects V _r2 = V _r1 + V _max −V _min (2) when subtracting. To do. However, V _min is defined by the difference voltage between the voltage at which the voltage reference V _r1 generates the minimum pulse width and the maximum voltage V _{max as} compared with the virtual carrier C _a1 . Therefore, since the control cycle T ₁ is addition, the up / down counter is preset to the point P ₁ by the voltage reference V _{r2 according} to the equation (1) and incremented every clock pulse. And the count value is V
_When it exceeds _max , the gate signal G _P is changed from "0" to "1". Since the control cycle T ₂ is a subtraction, it is preset to the point P ₂ by the voltage reference V _{r2 according} to the equation (2) and decremented every clock pulse, and when the count value becomes V _max or less, the gate signal G _{P is set} to "0". . Hereinafter, the control cycle T ₃ ,
The same is repeated at T ₄ . However, in the control cycle T ₅ , the timing pulse INT ₂ is selected by the switching timing selection unit 5 as in the first embodiment, and preset at the point P ₅ by the voltage reference V _r2 . That is, when the timing pulse INT ₂ is selected, the voltage reference conversion unit 23 outputs the signal C from the switching timing selection unit 5.
The voltage reference is corrected by H as follows.

When performing addition, V _r2 = V _r1 -V _min (3) When performing subtraction, V _r2 = V _r1 + V _max + V _min (4) Therefore, in the control cycle T ₅ , up and down is performed at the timing of INT _2. The count of the counter starts and the count value is V _max.
It is possible to prevent the time T _min before exceeding Tm from becoming less than the minimum pulse width.

[0018]

According to the present invention, the gate signal having the minimum pulse width can be secured without slowing the response of the control system and without lowering the voltage utilization factor.
When applied to an inverter, the voltage utilization factor is further improved, and an inverter device using PWM control with improved performance can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the first embodiment.

FIG. 3 is a time chart for explaining the operation of the first embodiment.

FIG. 4 is a configuration diagram of main parts of a second embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of the second embodiment.

FIG. 6 is a main circuit configuration diagram of an NPC inverter.

FIG. 7 is a time chart for explaining the problems of the conventional device.

FIG. 8 is a general composition of a PWM inverter main circuit.

FIG. 9 is a configuration diagram of main parts of a conventional device.

[Description of Codes] 1 ... Controller 2 ... Carrier generation circuit 3, 22 ... Switching timing generation unit 4 ... Switching timing delay circuit 5 ... Switching timing selection unit 6, 24 ... PWM circuit 7 ... Carrier phase shift circuit 8 ... Switch 10 ... Inverter 11 ... Motor 12 ... Speed detector 13 ... DC power supply 21 ... Clock generator 23 ... Voltage reference converter

Claims (4)

[Claims] 1. A controller for updating a voltage reference with a half cycle of the pulse width modulation cycle as a control cycle, and a pulse width modulated signal comparing a triangular wave carrier having the pulse width modulation cycle with the voltage reference. -In an inverter device having a comparator for generating a pulse signal, a timing for defining a timing point of a leading edge and a trailing edge of a predetermined minimum pulse width by comparing the carrier with upper and lower threshold values The generating means and the timing selecting means for setting the update timing of the voltage reference input to the comparator according to the value of the voltage reference for each control cycle to the timing point of either the leading edge or the trailing edge are provided. An inverter device using PWM control characterized by the above. 2. The inverter device using PWM control according to claim 1, wherein the timing selection means has a voltage reference of a previous control cycle exceeding a range of the upper and lower threshold values, and When the voltage reference of the control cycle falls within the range of the upper and lower thresholds, the timing of updating the voltage reference input to the comparator is set to the timing point of the leading edge, and otherwise the trailing edge An inverter device using PWM control, which is characterized by timing. 3. An inverter provided with a controller for updating a voltage reference with a half cycle of the pulse width modulation cycle as a control cycle, and means for outputting a gate signal pulse width modulated according to the voltage reference. In the apparatus, a timing pulse generating means for generating a first timing pulse for each control cycle and generating a second timing pulse delayed from the generation time by a time obtained by subtracting a predetermined minimum pulse width from the control cycle. And timing selection means for selecting one of the first and second timing pulses according to the value of the voltage reference for each control cycle, and a predetermined value according to the voltage reference is preset by the selected timing pulse. The number of clock pulses with a constant period is counted in the mode of addition and subtraction alternately for each control period, and when a predetermined count value is exceeded, a predetermined logic An up / down counter for outputting a gate signal, and a preset value determination for correcting the preset value of the up / down counter in accordance with the addition / subtraction mode and the timing pulse selected by the timing selection means. An inverter device using PWM control, characterized in that means is provided. 4. The inverter device using PWM control according to claim 3, wherein the timing selection means is such that a voltage reference of a previous control cycle is an upper and lower limit threshold value that defines the minimum pulse width. When the voltage exceeds the range and the voltage reference of the current control cycle falls within the range of the upper and lower thresholds, the second
Timing pulse is selected, otherwise the first
PWM characterized by selecting the timing pulse of
Inverter device using control.