JP2003088131A - Pwm circuit and inverter using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems of a PWM circuit of the system which changes frequency of the carrier without relation to signal wave and time and reduces magnetic sound and mechanical vibration of the apparatus, that expensive V/F converter and D/A converter are required for changing the frequency, and that aging and temperature changes are large resulting in unstable condition because an analog signal process which changes frequency is included. SOLUTION: This PWM circuit is provided with an amplitude command register 17 in order to simultaneously change in the same rate an amplitude of carrier (triangular wave) and an amplitude of voltage signal. A value set to this register 17 determines (changes) the amplitude of carrier and change continuously this amplitude. Meanwhile, since a voltage changing rate (slope of waveform) of the carrier is determined to the constant value depending on the frequency of an oscillator 4 counted by an up/down counter 5, change of amplitude provides the same effect as that when the frequency is changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM circuit for controlling on / off operations of main circuit elements of an inverter device and an inverter device using this PWM circuit.

[0002]

2. Description of the Related Art In an inverter device of a power conversion system, a circuit for generating a signal (hereinafter referred to as a gate pulse) for controlling on / off of a semiconductor element which constitutes a main circuit of the inverter is provided with a triangular wave comparison PWM (Pulse Width).
th Modulation, also called pulse width modulation)
Circuits are commonly used. In the triangular wave comparison PWM circuit,
The triangular wave is a carrier wave, the voltage command value is a signal wave, the switching time of the power semiconductor is determined by the magnitude of the triangular wave and the voltage command value, and the output voltage of the inverter can be controlled by changing the voltage command value. In this type of triangular wave comparison PWM circuit, the frequency of the triangular wave is generally constant, and the voltage command value is a sine wave signal. However, in such a self-excited inverter device, a circuit such as a reactor used in the device is used. Magnetic noise or mechanical vibration having a carrier frequency as a fundamental frequency is generated from the element. As a measure for reducing the magnetic noise, a method of temporally changing the frequency of the triangular wave regardless of the voltage command value wave is used.

FIG. 19 shows, for example, the Institute of Electrical Engineers of Japan Technical Report No. 59.
6 shows a PWM circuit unit of a conventional self-excited inverter device shown in No. 6 (July 1996). In the figure, 1 is a CPU
(Central processing unit), 2 is a voltage command register for storing a voltage command (signal wave) output from the CPU 1. Generally, a sinusoidal signal corresponding to the voltage waveform to be output from the self-exciting inverter is output from the CPU 1 to the voltage command register 2. A D / A converter 3 outputs an analog signal according to a command from the CPU 1. A V / F converter 34 outputs a pulse train having a frequency proportional to the analog signal input from the D / A converter 3. An up / down counter 5 counts the pulse train output from the V / F converter 34 to generate a triangular wave as a carrier wave. Reference numeral 6 denotes a comparator, which compares the values of the up / down counter 5 and the voltage command register 2 and determines the switching time of the power semiconductor depending on the size of the comparator, and controls the output voltage of the inverter by changing the signal wave. .

Next, the operation will be described. As shown in FIG. 20, the CPU 1 outputs to the voltage command register 2 a sinusoidal signal wave 100 corresponding to the voltage waveform to be output from the self-excited inverter. On the other hand, from CPU1 to D /
By giving a command to the A converter 3, an analog signal corresponding to the command is output. A pulse train having a frequency proportional to the voltage value that receives the analog signal is output from the V / F converter 34. The up / down counter 5 counts a pulse train from the V / F converter 34 to form a triangular wave (also referred to as a carrier) 101.
To generate. The comparator 6 compares the triangular wave 101 output from the up / down counter 5 with the output 100 of the voltage command register 2. When the value of the voltage command register 2 is greater than the value of the triangular wave up / down counter, 1 is output from the comparator 6, and 0 in the opposite case.
Is output. This signal is shown as 102 in the figure.

As shown at 102 in FIG. 20, a triangular wave 10
When the frequency of 1 is constant and the signal wave 100 is changed in a sine wave shape, the ratio between the period of 1 and the period of 0 of the signal 102 output from the comparator 6 becomes longer depending on the magnitude of the signal wave 100. It gets shorter. It is known that it is effective to temporally change the frequency of the carrier wave 101 in order to reduce the magnetic noise and mechanical vibration of the inverter device. For example, the clock frequency input to the up / down counter 5 is changed. It can be realized by To that end, in the above configuration, the command given from the CPU 1 to the D / A converter 3 is changed irrespective of the signal wave,
The frequency of the pulse train output from the V / F converter 34 is changed. As a result, the frequency of the triangular wave generated by the up / down counter 5 by counting the pulse train changes.

However, in this configuration, the D / A converter 3
It is necessary to use relatively expensive components that can cope with a wide range of frequency changes, such as the V and F / F converters 34. Furthermore, since an analog signal is interposed in the processing circuit, the values of the resistors and capacitors used change due to temperature changes and changes over time, and the frequency stability of the carrier wave cannot be obtained sufficiently. .

[0007]

As described above, the PWM of the conventional method of changing the frequency of the carrier wave (triangular wave) regardless of the phase and magnitude of the signal wave and reducing the magnetic noise and mechanical vibration of the device. The circuit requires expensive parts, and since an analog signal is present, temperature changes and
There is a problem that the state is likely to change under the influence of changes over time.

The present invention has been made to solve the above problems, and provides a PWM circuit that does not use an expensive converter and does not interpose an analog signal.

[0009]

A PWM circuit according to the present invention includes a CPU that outputs a data string of a waveform signal that serves as a reference of an output voltage waveform of an inverter device, and a data string of the waveform signal that is held by the CPU. A voltage command register that converts the voltage signal data of the commanded size and outputs at the required timing, an oscillator that oscillates a pulse of a predetermined frequency that is determined in advance, the pulse train is up-counted or down-counted, and this count number Each time the upper limit value commanded by the CPU is reached or becomes zero, an up / down counter that generates carrier wave data by switching the count direction, the carrier wave data is compared with the voltage signal data, A comparator for outputting a binary signal corresponding to the magnitude as a gate pulse signal of the inverter device; According to a command from the PU, an amplitude command register for simultaneously changing the upper limit value of the up / down counter and the voltage signal data of the voltage command register at the same rate is provided, and the gate pulse is generated by the amplitude command register. The frequency of the carrier wave data is changed while keeping the duty ratio of the signal constant.

Further, a CPU which outputs a data string of a waveform signal serving as a reference of an output voltage waveform of the inverter device, holds the data string of the waveform signal, and converts it into voltage signal data of a size instructed by the CPU. Then, a voltage command register that outputs at a necessary timing, an oscillator that oscillates a pulse having a predetermined frequency, and the pulse train is up-counted or down-counted, and this count reaches the upper limit value commanded by the CPU. Each time it becomes zero or zero, an up / down counter that generates carrier wave data by switching the count direction, the carrier wave data and the voltage signal data are compared, and a binary signal according to the magnitude is compared with the inverter. Comparator for outputting as gate pulse signal of device, current count of the up / down counter And wherein with the current count change register rewritten forced to a new value which is set below the upper limit by the CPU, and changes the phase of the carrier wave data by the current count change register.

Further, a CPU that outputs a data string of a waveform signal that serves as a reference of an output voltage waveform of the inverter device, holds the data string of the waveform signal, and converts it into voltage signal data of a size instructed by the CPU. Then, a voltage command register that outputs at a necessary timing, an oscillator that oscillates a pulse having a predetermined frequency, and the pulse train is up-counted or down-counted, and this count reaches the upper limit value commanded by the CPU. Each time it becomes zero or zero, an up / down counter that generates carrier wave data by switching the count direction, the carrier wave data and the voltage signal data are compared, and a binary signal according to the magnitude is compared with the inverter. Comparator for outputting as gate pulse signal of device, current count of the up / down counter The adder to be outputted to the comparator by adding the commanded value, an addition register for commanding the value to the adder according to the command of the CPU,
The adder register changes the phase of the carrier wave data.

A second addition register for holding the output of the addition register and inputting the held value to the adder at a timing when the output of the comparator satisfies a predetermined specific condition. Be prepared.

Further, the predetermined specific condition is that the magnitude of the carrier signal is larger than the magnitude of the voltage signal.

Further, during a period in which the exclusive OR of the most significant bit of the carrier wave data and the most significant bit of the voltage signal data is 1, the value of the addition register is set to the second addition value. The timing generator circuit outputs a trigger signal to be input to the adder via a register.

Further, the value of the addition register is set to the second value.
The output of the adder in which the output of the up-down counter is larger than the voltage signal and the value of the phase register is added to the up-down counter, and the trigger signal which is held in the addition register and moved to the adder Is provided with a second timing generation circuit for generating the voltage in a period larger than the voltage signal.

An inverter device according to the present invention is one in which magnetic noise generated from a circuit element constituting the inverter device is reduced by using any one of the PWM circuits described above.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. The PWM circuit according to the first embodiment of the present invention will be described below with reference to FIG.
In FIG. 1, reference numeral 1 is a CPU, which outputs to a voltage command register 2 a data string of a waveform signal serving as a reference of a voltage command value which is a PWM modulation value for commanding a waveform of an output voltage of an inverter. . Reference numeral 4 denotes an oscillator, which generates a pulse (clock) having a predetermined frequency as a source for generating a triangular wave which is a carrier wave of PWM. Upon receiving a signal from the oscillator 4, an up / down counter (also referred to as an up / down counter) 5 performs an up or down count operation, and counts up to a value set in the amplitude command register 17 set by the CPU 1. When it reaches the upper limit value, it shifts to a countdown operation, counts down to zero, and repeats thereafter. The count value of the up / down counter 5 becomes the amplitude data of the triangular wave which is the PWM carrier wave of the inverter, and is compared with the output of the voltage command register 2 which is the voltage command value data (voltage signal) by the comparator 6. The comparator 6 compares the triangular wave with the voltage command value, and outputs 1 when the voltage command value is larger than the triangular wave, and outputs 0 when the voltage command value is smaller (outputs a binary signal). This output becomes a gate pulse of the power semiconductor of the inverter and controls the output of the inverter.

For example, the value of the amplitude command register 17 is 40
In the case of 95, the up / down counter 5 receives the signal of the oscillator 4 and performs an up operation from 0 to 4095.
When it reaches 0, the down operation is performed to 0 to generate a triangular wave which is a carrier wave. Therefore, in order to set the carrier frequency to 10 KHZ, 4096 × 2 × from the oscillator 4
It is necessary to generate a frequency of 10 KHZ. Here, when the value of the amplitude command register 17 is set to 2047, the value of the up / down counter 5 is folded back at 2047, and the frequency of the signal generated from the oscillator 4 is the same as the above 4096 × 2 × 10 KHZ. , The carrier frequency is (4096 × 2 × 10) / (2048 × 2) KH
Z = 20KHZ.

As described above, by changing the peak value of the carrier wave, that is, the amplitude of the carrier wave, the frequency of the carrier wave can be changed even if the frequency of the oscillator 4 is the same. However, if the value of the voltage command register 2 that stores the voltage command value remains the same before and after the change of the carrier peak value, the pulse width output from the comparator 6 (the time ratio between the period of 1 and the period of 0). ) Will change, and 1 may continue in some cases. Therefore, the amplitude command register 17 changes the peak value of the carrier wave and also changes the voltage command value which is the output of the voltage command register 2 at the same rate as the change.

In order to facilitate understanding, the above description will be described again using the waveforms in FIG. In FIG. 2, 110 is a triangular wave carrier, 110a is a triangular wave, and 110b is a triangular wave, and its amplitude is 2047.
belongs to. For example, when the carrier peak is 4095, the ratio of the time lengths of 1 and 0 output from the comparator 6 is set to 25:75 (the duty ratio is 25/100.
1024 in the voltage command register 2
(Where 1024 is obtained from 4095 × 25 / (25 + 75)). The carrier frequency in this case is 10 KHZ. If the carrier peak value is changed to 2047 as shown in the right part of the figure, the carrier frequency becomes 20 KHZ. Here, if the voltage command value remains 1024, the output ratio of 1 and 0 from the comparator 6 becomes 50: 5 as in 112b of FIG.
0 (50 is obtained from 1024/2047 × 100)
become. Therefore, the amplitude command register 17 changes the output voltage command value of the voltage command register 2 to 512 at the same time when the up / down counter 5 is changed, so that
As shown in FIG. 12C, the output time ratio of 1 and 0 output from the comparator 6 can be maintained at 25:75 (that is, the duty ratio can be kept constant). As mentioned above,
By simultaneously changing the amplitude command register 17 and the voltage command register 2 at the same rate, the carrier frequency can be arbitrarily changed while keeping the duty ratio of the gate pulse constant. With this configuration, the carrier frequency can be changed without interposing an analog signal, and a PWM circuit that is stable over time and temperature can be realized.

Embodiment 2. By suddenly changing the phase of the carrier wave having a constant frequency, it is possible to obtain a gate pulse signal similar to that in which the frequency of the carrier wave is changed. For example, advancing the carrier phase is similar to increasing the carrier frequency, and conversely, delaying the phase is similar to decreasing the frequency. That is, in FIG. 3, 120 is a carrier wave whose phase is changed midway (points A and B).
When the phase is advanced at the point A of the carrier wave 120, the gate pulse signal is similar to the case where the frequency of the triangular wave 120 is increased, as shown at 121, and conversely, when the phase is delayed at the point B, the frequency is decreased. Become.

FIG. 4 shows the configuration of a PWM circuit capable of adjusting the phase of the carrier wave as described above. In FIG.
Reference numeral 1 is a CPU, 2 is a voltage command register, 4 is an oscillator for generating a clock for generating a triangular wave that is a PWM carrier wave, and 5 is an up / down counter for generating a triangular wave. The up / down counter 5 is presettable, and the value of the current count number changing register 27 is forcibly set in the up / down counter 5 at a commanded timing, and the up / down counter 5 changes from the value. Continue counting operation.

In FIG. 4, at the timing when the CPU 1 sets data in the current count number changing register 27, the count number of the up / down counter 5 is rewritten to the value of the current count number changing register 27, and the value is increased from that value. / The down counter 5 continues to count up or down. That is, as shown in FIG. 5, the value of the up / down counter 5 at the time of setting a new value in the current count number changing register 27 (point A in the figure) is the new count value changing register 27 value. If it is different from this value, it means that the phase is changed rapidly and the frequency is equivalently changed. Of course, if the value of the up / down counter 5 at the time of setting a new value in the current count number changing register 27 happens to be the same as the new value in the current count number changing register 27, the phase does not change. The carrier wave will continue to have the same phase and frequency.

As shown in FIG. 6, for example, in the case of the up / down counter 5 whose carrier wave peak is 4095, when the value of the up / down counter 5 is 1024 (A in the figure).
If 2048 is set in the current count number changing register 27 at (point), it means that the phase has changed by 45 °. Same 4
If you want to change 5 °, up / down counter 5
When the value of is 3072 (point B in the figure), it can be realized by setting 4095 in the current count number changing register 27.

Therefore, while always detecting the current value of the up / down counter 5, a new value different from the value of the up / down counter 5 (a value corresponding to a desired phase difference) is changed to the current count number changing register. By setting it to 27, the phase can be changed to an arbitrary value.

Embodiment 3. In the second embodiment, the CPU
The current value of the up / down counter must always be detected before the 1 changes the carrier frequency. If this is not the case, even if the same numerical value is set, the advance and the delay may have opposite results. Therefore, FIG. 7 shows a configuration of a PWM circuit improved in this point. In FIG. 7, 1 is a CPU, 2 is a voltage command register, 4 is an oscillator, 5 is an up / down counter, and 7 is an addition register. The up / down counter 5 is initially set
It is assumed that count-up or count-down is set and an arbitrary count value is set. For example, when the up operation and a certain arbitrary count value α are set, the count value α is counted up, the countdown is started when the maximum count value is reached, and the countup is started when the minimum count value is reached. That is, the up / down counter 5 is a counter that repeats the count-up / down operation from the initially set value. The addition register 7 is a register for adding or subtracting an arbitrary value to the value of the counter 5 in order to change the phase of the carrier wave.

The adder / subtractor 8 is an adder / subtractor (adder referred to in the present invention) that operates as an adder when the up / down counter 5 counts up and operates as a subtracter when countdown operates. CPU in this invention
When the data is set in the addition register 7 by 1, the value of the addition register 7 is added to or subtracted from the value of the counter by the adder / subtractor 8. The value added / subtracted by the adder / subtractor 8 becomes the PWM carrier wave.

As shown in FIG. 8, for example, when the count-up / down operation is repeatedly performed by the up / down counter whose carrier wave peak is 4095, the CPU
When data of an arbitrary change amount (α in the figure) is set from 1 to the addition register 7, the data of the addition register 7 is added by the adder / subtractor 8 during the count-up operation,
The phase changes forward. The phase can be returned to the original state by newly setting 0 in the addition register 7. The phase delay can be realized by newly setting a negative value in the addition register 7.

Further, as shown in FIG. 9, for example, in the countdown operation, when the data of the arbitrary change amount β is set in the addition register 7 from the CPU 1, β is subtracted by the adder / subtractor 8 to advance the phase. Changes to. To return the phase to the original value, 0 is newly set in the addition register 7, and to realize the phase delay, a new negative value is set in the addition register 7. Therefore, even if the value of the up / down counter 5 is not always detected,
By setting the value in the register 7 for addition, the phase of the carrier wave can be changed to lead or lag by the adder / subtractor 8.

Fourth Embodiment FIG. 10 illustrates a case where the phase of the carrier is advanced as in the second or third embodiment in order to help understanding of the present embodiment.
Carrier wave 119 before advancing the phase and carrier wave 1 after advancing the phase
20, and the signal waves 122 and 123 corresponding to each
In this case, when the phase change is instructed at the time C shown in FIG. 10, change amount data is set in the addition register 7, and when the phase changes forward, the gate pulse 122 before the phase change Gate pulse after phase change 1 compared to width
Since the width of 23 is changed only in the portion 125 shown in the figure, there is a problem that the originally required gate pulse width cannot be secured, that is, the duty of the gate pulse cannot be held constant.

Therefore, FIG. 11 shows the configuration of a PWM circuit in which such a point is improved. In FIG. 11, CPU1
Sets the phase change amount data in the addition register 7. Reference numeral 9 is a second addition register in which the value of the addition register 7 is set by a trigger signal described later. Since the initial value of the value of the second addition register 9 is 0, the output of the adder / subtractor 8 is the data of the up / down counter 5,
It is the carrier wave of the PWM signal as it is. Adder / subtractor 8
As a result of the comparison between the data of No. 2 and the data of the voltage command register 2 by the comparator 6, the timing when the carrier wave is larger (that is, the gate pulse is 0) is used as a trigger, and the data of the addition register 7 is used for the second addition. Set in register 9. That is, in FIG. 12, when the data of the adder / subtractor 8 and the data of the voltage command register 2 are compared by the comparator 6 and it is determined that the data of the adder / subtractor 8 is larger (that is, the gate pulse is output). The pulse width of the gate pulse can be held by adding the value of the second addition register 9 by the adder / subtractor 8 (when there is no such).

Fifth Embodiment In the configuration of the fourth embodiment,
There is no problem when advancing the phase, but when delaying the phase, as shown in FIG. 13, depending on the timing,
As a result of the delay, the carrier wave 120 becomes lower than the voltage signal 100, and an incorrect gate pulse 126 may be generated again after the normal gate pulse ends. Therefore, in the present embodiment, as shown in FIG. 14, the data of the adder / subtractor 8 and the data of the voltage command register 2 are input to the timing generation circuit 10. The operation of the timing generation circuit 10 will be described. Adder / subtractor 8
13 and the data of the voltage signal 100 output from the voltage command register 2 are represented by n digits (for example, 12 digits) of a binary number, 0 in FIG. From the level to the level of 2047, the above-mentioned 12-digit most significant bit is 0. And
From 2048 to 4095 levels, the 12 most significant bits are 1.

Therefore, the timing generation circuit 10 takes the exclusive OR of the most significant bit values of the data of the adder / subtractor 8 (carrier wave 120) and the data of the voltage command register 2 (voltage signal 100). The trigger signal is output to the second addition register 9 only at the timing when the result is 1. Table 1 shows this.

[0034]

[Table 1]

Table 1 is shown in FIG.
As a result, the command for changing the phase is not output before and after the rising point and the falling point of the gate pulse, and the generation of the extra pulse 126 as shown in FIG. 13 is prevented. The value of the register 7 for addition is set as the data of the second register 9 for addition by the trigger signal. The data of the second addition register 9 is added to the adder / subtractor 8
The incorrect pulse generated in FIG. 13 can be prevented by adding the value in FIG. 13. Therefore, as shown in FIG. 16, the phase is changed at a position avoiding the vicinity of the rising and falling edges of the gate signal, and the incorrect pulse 126 is generated. The phase can be changed without being generated.

Sixth Embodiment In the configuration of the fourth embodiment,
Although there is no problem when advancing the phase, when delaying the phase, as shown in FIG. 13 of the fifth embodiment, if the phase is delayed only by the condition of carrier 120> voltage signal 100, the carrier 120 is delayed as a result. The voltage may be lower than the voltage signal 100 and an incorrect gate pulse 126 may be generated. Therefore, as shown in FIG. 17, the data of the up / down counter 5 (carrier wave before addition / subtraction), the data of the adder / subtractor 8 (carrier wave after addition / subtraction), and the data of the voltage command register 2 are set at the second timing. Generation circuit 3
Output to 0. The second timing generation circuit 30 compares the data of the up / down counter 5 (carrier wave before addition / subtraction) with the data of the voltage command register 2 and outputs 1 when the carrier wave is larger. A comparator 30a,
Compare the data of the adder / subtractor 8 (carrier after addition / subtraction) with the size of the voltage command register 2 and if the carrier is larger, 1
A second comparator 30b that outputs a signal and an AND circuit that outputs a signal when both the outputs of the first and second comparators are 1.

This signal is output to the second addition register 9 as a trigger signal. The value of the addition register 7 is set as the data of the second addition register 9 by the trigger signal. The data in the second addition register 9 is added to the adder / subtractor 8
It is possible to prevent the above-mentioned incorrect pulse 126 by adding and subtracting with. FIG. 18 is a waveform diagram showing the above state. In the figure, reference numeral 130 indicates a time range in which both the carrier wave before addition and subtraction and the carrier wave after addition and subtraction are larger than the signal wave 100, and the second timing generation circuit 30 outputs a trigger signal within this range 130. Therefore, FIG.
As shown in, the phase can be changed without generating the incorrect pulse 126. In the inverter device configured by using any of the PWM circuits of the first to sixth embodiments described above, by changing the frequency or the phase of the carrier wave arbitrarily, the magnetic field of the reactor or the like used in the inverter device can be changed. The sound becomes irregular, and it can be expected to reduce noise.

[0038]

As described above, in the PWM circuit of the present invention, the carrier wave (triangular wave) is generated by the up-down counter that counts a constant frequency, and its slope is kept constant.
Since the frequency of the gate pulse is changed by changing its amplitude, the circuit configuration is digitized, and simple and stable performance can be obtained.

Since the current count number changing register for forcibly rewriting the count value of the up / down counter is provided, the phase of the carrier wave can be changed,
The same effect as apparently changing the frequency can be obtained.

Further, since the adder for adding the value of the phase register to the output of the up / down counter is provided and the count value of the up / down counter can be arbitrarily changed, the phase of the carrier wave can be changed and the apparent frequency can be changed. You can obtain the same effect as changing.

Further, since the second addition register for adding the value of the addition register to the count value of the up / down counter is provided when the output of the comparator satisfies a predetermined specific condition, It is possible to prevent the output of an extra gate pulse and the shortage of the gate pulse when changing.

The predetermined condition does not affect the pulse width of the gate pulse because the carrier signal is larger than the voltage signal, that is, the timing when the gate pulse is not output.

Since the timing at which the value of the addition register is held in the second addition register is generated from the output of the adder / subtractor and the value of the voltage command register, the output of an extra gate pulse when changing the phase Can be prevented.

The timing at which the value of the register for addition is held in the second register for addition is generated from the timing at which both the carrier wave before addition and the carrier wave after addition become larger than the value of the voltage command register. Therefore, when changing the phase, output of extra gate pulse and shortening of gate pulse,
You can prevent the extension.

The inverter device of the present invention has the above-mentioned PW.
Since any of the M circuits is used, it is possible to reduce the magnetic sound generated from the circuit elements that form the inverter device.

[Brief description of drawings]

FIG. 1 is a block diagram of a PWM circuit according to a first embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of FIG.

FIG. 3 is an explanatory diagram illustrating a frequency change caused by changing a phase of a carrier wave.

FIG. 4 shows a block diagram of a PWM circuit according to a second embodiment of the present invention.

5 is a timing diagram illustrating the operation of FIG.

FIG. 6 is a timing diagram illustrating the operation of FIG.

FIG. 7 shows a block diagram of a PWM circuit according to a third embodiment of the present invention.

FIG. 8 is a timing diagram illustrating the operation of FIG.

FIG. 9 is a timing diagram illustrating the operation of FIG. 7.

FIG. 10 shows a timing diagram illustrating the problem of the operation of FIG.

FIG. 11 shows a block diagram of a PWM circuit according to a fourth embodiment of the present invention.

FIG. 12 shows a timing diagram illustrating the operation of FIG.

FIG. 13 shows a timing diagram illustrating the problem of FIG.

FIG. 14 is a PWM circuit block diagram according to the fifth embodiment of the present invention.

FIG. 15 shows a timing diagram illustrating the operation of FIG.

16 shows a timing diagram illustrating the operation of FIG.

FIG. 17 is a PWM circuit block diagram according to the sixth embodiment of the present invention.

FIG. 18 shows a timing diagram illustrating the operation of FIG.

FIG. 19 is a block diagram of a conventional PWM circuit.

FIG. 20 is a timing explanatory diagram illustrating the operation of FIG. 19;

[Explanation of symbols]

1 CPU, 2 voltage command register, 3 D
/ A converter, 4 oscillators, 5 up / down counters, 6 comparators, 7 addition registers,
8 adder / subtractor, 9 second adder register, 10
Timing generation circuit, 17 amplitude command register,
27 current count number changing register, 30 second timing generation circuit, 100 voltage signal, 110 carrier wave (triangular wave), 112 gate pulse signal, 11
9 carrier wave before phase change, 120 carrier wave with changed phase, 121 gate pulse signal corresponding to phase change.

Claims (8)

[Claims] 1. A CPU that outputs a data string of a waveform signal that serves as a reference of an output voltage waveform of an inverter device, holds the data string of the waveform signal, and converts the data into voltage signal data of a size instructed by the CPU. Then, a voltage command register that outputs at a required timing, an oscillator that oscillates a pulse having a predetermined frequency, and up-counts or down-counts the pulse train,
An up / down counter that generates carrier wave data by switching the count direction each time the count number reaches the upper limit value instructed by the CPU or becomes zero, and compares the carrier wave data with the voltage signal data. And a comparator that outputs a binary signal corresponding to the magnitude as a gate pulse signal of the inverter device, the upper limit value of the up / down counter and the voltage signal of the voltage command register according to a command from the CPU A PWM characterized by including an amplitude command register for simultaneously changing the data and the data at the same rate, and changing the frequency of the carrier wave data while keeping the duty ratio of the gate pulse signal constant by the amplitude command register.
circuit. 2. A CPU that outputs a data string of a waveform signal that serves as a reference of an output voltage waveform of an inverter device, holds the data string of the waveform signal, and converts it into voltage signal data of a size instructed by the CPU. Then, a voltage command register that outputs at a required timing, an oscillator that oscillates a pulse having a predetermined frequency, and up-counts or down-counts the pulse train,
An up / down counter that generates carrier wave data by switching the count direction each time the count number reaches the upper limit value instructed by the CPU or becomes zero, and compares the carrier wave data with the voltage signal data. A comparator for outputting a binary signal corresponding to the magnitude as a gate pulse signal of the inverter device;
A current count number changing register for forcibly rewriting to a new value set below the upper limit value by the PU,
A PWM circuit characterized in that the phase of the carrier wave data is changed by the current count number changing register. 3. A CPU that outputs a data string of a waveform signal that serves as a reference of an output voltage waveform of an inverter device, holds the data string of the waveform signal, and converts it into voltage signal data of a size instructed by the CPU. Then, a voltage command register that outputs at a necessary timing, an oscillator that oscillates a pulse of a predetermined frequency, and up-counts or down-counts the pulse train,
An up / down counter that generates carrier wave data by switching the count direction each time the count number reaches the upper limit value instructed by the CPU or becomes zero, and compares the carrier wave data with the voltage signal data. Then, a comparator that outputs a binary signal corresponding to the magnitude as a gate pulse signal of the inverter device, an addition that adds a commanded value to the current count value of the up-down counter and outputs the added value to the comparator A PWM circuit, comprising: an adder register for instructing the value to the adder based on an instruction from the CPU, and changing the phase of the carrier wave data by the adder register. 4. A second addition register that holds the output of the addition register and inputs the held value to the adder at a timing when the output of the comparator satisfies a predetermined specific condition. The PWM circuit according to claim 3, wherein the PWM circuit is provided. 5. The PW according to claim 4, wherein the predetermined specific condition is that the magnitude of the carrier signal is larger than the magnitude of the voltage signal.
M circuit. 6. The most significant bit of the carrier data,
While the exclusive OR of the voltage signal data and the most significant bit is 1, the value of the addition register is set to the second value.
5. The PWM circuit according to claim 4, further comprising a timing generation circuit that outputs a trigger signal to be input to the adder via the addition register of. 7. A trigger signal for holding the value of the adder register in the second adder register and moving it to the adder, wherein the output of the up / down counter is larger than the voltage signal and the up signal is up. 5. The PWM circuit according to claim 4, further comprising a second timing generation circuit that generates the output of the adder, which is obtained by adding the value of the phase register to the down counter, when the output of the adder is larger than the voltage signal. 8. An inverter device characterized in that magnetic noise generated from a circuit element forming an inverter device is reduced by using the PWM circuit according to any one of claims 1 to 7.