JPS6089772A - 集積回路素子実装ユニツトの試験方式 - Google Patents

集積回路素子実装ユニツトの試験方式

Info

Publication number
JPS6089772A
JPS6089772A JP58198632A JP19863283A JPS6089772A JP S6089772 A JPS6089772 A JP S6089772A JP 58198632 A JP58198632 A JP 58198632A JP 19863283 A JP19863283 A JP 19863283A JP S6089772 A JPS6089772 A JP S6089772A
Authority
JP
Japan
Prior art keywords
scan
system clock
integrated circuit
data
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58198632A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0452904B2 (cs
Inventor
Masayoshi Nakayama
中山 雅恵
Toshihiko Tada
多田 敏彦
Akira Kaneko
明 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58198632A priority Critical patent/JPS6089772A/ja
Publication of JPS6089772A publication Critical patent/JPS6089772A/ja
Publication of JPH0452904B2 publication Critical patent/JPH0452904B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/267Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP58198632A 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式 Granted JPS6089772A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58198632A JPS6089772A (ja) 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58198632A JPS6089772A (ja) 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式

Publications (2)

Publication Number Publication Date
JPS6089772A true JPS6089772A (ja) 1985-05-20
JPH0452904B2 JPH0452904B2 (cs) 1992-08-25

Family

ID=16394425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58198632A Granted JPS6089772A (ja) 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式

Country Status (1)

Country Link
JP (1) JPS6089772A (cs)

Also Published As

Publication number Publication date
JPH0452904B2 (cs) 1992-08-25

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