JPS6089772A - 集積回路素子実装ユニツトの試験方式 - Google Patents

集積回路素子実装ユニツトの試験方式

Info

Publication number
JPS6089772A
JPS6089772A JP58198632A JP19863283A JPS6089772A JP S6089772 A JPS6089772 A JP S6089772A JP 58198632 A JP58198632 A JP 58198632A JP 19863283 A JP19863283 A JP 19863283A JP S6089772 A JPS6089772 A JP S6089772A
Authority
JP
Japan
Prior art keywords
scan
integrated circuit
system clock
logic
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58198632A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0452904B2 (cs
Inventor
Masayoshi Nakayama
中山　雅恵
Toshihiko Tada
多田　敏彦
Akira Kaneko
明 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58198632A priority Critical patent/JPS6089772A/ja
Publication of JPS6089772A publication Critical patent/JPS6089772A/ja
Publication of JPH0452904B2 publication Critical patent/JPH0452904B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP58198632A 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式 Granted JPS6089772A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58198632A JPS6089772A (ja) 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58198632A JPS6089772A (ja) 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式

Publications (2)

Publication Number Publication Date
JPS6089772A true JPS6089772A (ja) 1985-05-20
JPH0452904B2 JPH0452904B2 (cs) 1992-08-25

Family

ID=16394425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58198632A Granted JPS6089772A (ja) 1983-10-24 1983-10-24 集積回路素子実装ユニツトの試験方式

Country Status (1)

Country Link
JP (1) JPS6089772A (cs)

Also Published As

Publication number Publication date
JPH0452904B2 (cs) 1992-08-25

Similar Documents

Publication Publication Date Title
US5115435A (en) Method and apparatus for bus executed boundary scanning
JPH0760400B2 (ja) 論理回路の診断方法
US5384533A (en) Testing method, testing circuit and semiconductor integrated circuit having testing circuit
US5831993A (en) Method and apparatus for scan chain with reduced delay penalty
US8341471B2 (en) Apparatus and method for synchronization within systems having modules processing a clock signal at different rates
JPS61155874A (ja) 大規模集積回路の故障検出方法およびそのための装置
JPS60239836A (ja) 論理回路の故障診断方式
JPS6089772A (ja) 集積回路素子実装ユニツトの試験方式
JP2002148310A (ja) 試験アーキテクチャ
GB2344184A (en) Testing integrated circuits
US20250155501A1 (en) Chip and chip testing method
US8281199B2 (en) Hybrid self-test circuit structure
US6973606B2 (en) Partially distributed control mechanism for scanout incorporating flexible debug triggering
JP3586609B2 (ja) 複数のスロットを持つボードの検査方式
JPH0391195A (ja) メモリ回路
US7020806B2 (en) Method for testing memory units to be tested and test device
JPH0566248A (ja) ３ステート回路のピンスキヤンイン方式
JP3080850B2 (ja) 半導体集積回路
KR200280380Y1 (ko) 메모리테스트장치
JP3125950B2 (ja) 特定用途向け集積回路
JPH0766030B2 (ja) 論理パッケージの診断方法
US20050058007A1 (en) Method for testing a circuit unit to be tested, and a test apparatus
SU1429117A1 (ru) Устройство дл анализа выходных реакций контролируемой цифровой схемы
JP2874984B2 (ja) デジタル論理装置のスキャン回路
JPH0464034B2 (cs)