JPS6088474A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the titled device of low resistance and high reliability by a method wherein isolated source, gate, and drain regions are formed on a semiconductor substrate, these regions being silicified, and poly Si being then used as the contact material with the silicide part. CONSTITUTION:After the gate, source, and drain regions are formed by a required method, a side wall 10 is formed by reactive ion etching. Next, the diffusion rate-determining type silicide 11 (Ti, Ta, Pt, etc.) of a small specific resistance is formed only at the parts of the source, gate, and drain. Then, poly Si is deposited, and the part 6 is doped with an impurity by excluding the high resistant part 7. At this time, the condition of heat treatment is chosen so that the metal silicide may be not completely stable; then, the increase in the contact resistance can be inhibited by reacting the metal with the upper poly Si of the part 6 on heat treatment after the poly Si deposition.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a low resistance gate and a low resistance contact.

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor device (one example is a two-layer polysilicon RAM with high load resistance). When polysilicon 6 in the figure was formed, an M oxide film was formed at the interface of the diffusion layer 3, resulting in a problem that the contact resistance was unstable and large. An object of the present invention is to eliminate this drawback and provide a low-resistance, high-reliability manufactured semiconductor device, and at the same time, it is possible to reduce the resistance of the gate electrode. The present invention will be explained below with reference to Examples.

(in the prescribed manner in Figure 2), the gate.

After forming the source and drain regions, the sidewalls 10' are etched by R (reactive ion etching).
t-form. Next, silicide 11 (T i , Ta , Pt
=) 'e, Shape only the source, gate, and drain parts. Next, the polysilicon is debossed, and 6 parts are doped with impurities except for 7 parts of the high resistance part. At this time, the heat treatment conditions were selected so that the metal silicide was not in a completely stable state, and in the heat treatment after polysilicon deposition, the metal reacted with the upper polysilicon of 6, resulting in an increase in contact resistance that was previously observed. was suppressed, resulting in a contact resistance of 2 to 11 Ω with a 2 μm contact. Since this structure is strong against penetration, it can be applied in addition to the high load resistance structure f(AM), and is a semiconductor device with an effective structure for realizing a high-speed, high-performance LSI.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a half-barrel body 113 according to the conventional method, and FIG. 2 is a cross-sectional view of a half-barrel body 16 of the present invention. Gate 5... Interlayer film 6... Doped polysilicon 7... High resistance polysilicon 8... Interlayer film 9... AL wiring 10... Sidewall 5ho2 11. [Phase] Silicide or higher Applicant: Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami

Claims (1)

[Claims] J. A step of forming separate source, gate, and drain regions on a semiconductor substrate, a step of siliciding the regions, and using a polysilicon portion as a contact material with the silicide portion. A semiconductor device featuring: 2. Ion implantation into the polysilicon portion, or
The semiconductor device according to claim 1, characterized in that the impurity is doped by thermal diffusion. 3. The polysilicon portion is formed by ion implantation or ii.
Consisting of a part doped with impurities by thermal diffusion and a part not diffused with impurities 'e4! ! F(a) Scope of extortion claims: Semiconductor devices listed in Section 1, 6.