JPS6081913A - Transversal filter - Google Patents

Abstract

PURPOSE:To decrease the number of connection pins of a tap coeficient setting element and reduce the tap area by constituting a circuit having the same performance with plural roll-off filters by using shift registers and one resistance block. CONSTITUTION:When a signal SQ from the Q output terminal of an FF15 is at a low level and variable terminsl of switch circuits 171-17n are conneced to A- side fixed contacts respectively, outputs of (n) stages of shift registers 13 are obtained at the movable terminals of the circuits 171-17n. Then, the output of a resistance block 18 which sums up the signals is supplied to sample holding circuits 211 and 212 and the sum signal sampled and held by the circuit 211 is outputted from a terminal 251. On the other hand, when the signal SQ is at a high level and the circuits 171-17n are connected to B-side fixed terminals, the sum signal obtained through the resistance block is supplied to the circuits 211 and 212 and the sum signal sampled and held by the circuit 212 is outputted from a terminal 251.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transversal filter suitable for use as a roll-off filter of a four-phase modulator, for example.

BACKGROUND TECHNOLOGY AND PROBLEMS It is known to modulate a carrier wave with a digital signal and use this to convert the digital signal into a signal within a given frequency band for transmission. FIG. 1 shows a four-phase modulator that performs phase modulation using four phases in such digital modulation.

In the figure, terminal (1) has a digital signal, for example N
An RZ signal is supplied, and this is supplied to the serial/parallel conversion circuit (2). Then, signals S and S2 are obtained by alternately taking one bit of each digital signal from the conversion circuit (2) of Jin.
is obtained. These signals S1 and S2 are band-limited by roll-off filters (3) and (4) and then supplied to balanced modulators (5) and (6). Then, the balanced modulator (5) is supplied with the carrier wave ωct, and this carrier wave si
nωct is modulated by signal SL. This modulated signal is supplied to an adder (7). On the other hand, the balanced modulator (6)
There is a carrier wave■ω. t is supplied, and this carrier wave part ωt is modulated by the signal S2. This modulated signal is sent to an adder (7
). Then, in the adder (7), the modulated signals from the balanced modulators (5) and (6) are added,
A four-phase modulation number 54P8K is obtained as the output.

The roll-off filter (3
) and (4) are exactly the same.

As the roll-off filters (3) and (4), transversal filters as shown in FIG. 2 are used.

In the figure, (81) to (sn-1) are each stage of a shift register, RO"Rn-1 is a resistor, (9) is an adder, and 0I is a Rono mother filter. Such transversal In filters, as is well known, r
Co-cn-1-6 by setting the resistance value of tn~Rn-1
The tap coefficients obtained are obtained, and a filter with an innolith response such as hk = audience CNX(ks) is realized. Here, if the tap coefficients CN are made symmetrical, an amplitude control filter with a constant delay is obtained, and if the tap coefficients CN are made antisymmetrical, a phase control filter with a constant amplitude is obtained. Roll-off filters (3) and (4) described above
The former is used as

By the way, in order to set the roll-off rate to 30% or less in the transversal filter shown in FIG. becomes very expensive. 4 in Figure 1
Since the phase modulator requires two such expensive transversal filters, it has the drawback of increasing costs accordingly.

OBJECTS OF THE INVENTION The present invention has been made in view of the above points, and as described above, it is an object of the present invention to reduce the cost of a transversal filter used as a roll-off filter of a four-phase modulator, for example.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention has two tap groups.
A delay system of more than one system, a multiplexer for switching each tag group of this delay system, a tap coefficient setting element connected to each output side of this multiplexer, and an output from each of the tap coefficient setting elements. This is similar to means for adding and means for separating the added output into two or more systems in association with the multiplexer.

Therefore, the expensive tap coefficient setting element is also used, and the cost can be reduced.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. This example is an example in which the filters are used as roll-off filters (3) and (4) of a four-phase regulator shown in FIG.

In the figure, 0° C. and (2) are input terminals to which signals s1 and s2 obtained from the serial-to-parallel conversion circuit (2) (see FIG. 1) are respectively supplied. These signals S1 and S2 are force signals as shown in FIG. 4B and C, respectively, when the digital signal applied to terminal (1) (see FIG. 1) is as shown in FIG. 4A.

The signal S1 supplied to the terminal 0°C is (131) to (13
n) is supplied to the n-stage shift register (6). On the other hand, the signal S2i! supplied to the terminal α! :, (14t)~
(14n) is supplied to the n-stage shift register (b).

Also, aυ is a D flip-flop, and the lock signal (bit clock) is output from terminal 0 as shown in the fourth diagram.
5CLK is supplied, and its Q output terminal and 6 output terminal receive signals SQ and S as shown in FIG. 4 E and F, respectively.
4 is obtained.

The signal sQ obtained at the Q output terminal is supplied as a clock signal to the shift registers α and (14), and the shift registers Q3 and α→ are configured to shift at the falling edge of the signal sQ.

Further, the outputs of the n stages (131) to (13n) of the shift register Q1 are supplied to the fixed terminals on the A side of the switch circuits (171) to (17n) constituting the multiplexer, respectively, while the outputs of the shift register Q→ (141) ~ (14n)
The outputs of the n stages of are connected to switch circuits (171) to (17), respectively.
n) is supplied to the fixed terminal on the B side. Switch circuit (1
71) to (t7n), the signal sQ obtained at the Q output terminal of the flip-flop ◇0 is supplied as a switching control signal. When the signal sQ is at a low level, each is switched to the A side, and outputs of n stages (lh) to (13n) of the shift register Q3 are obtained at each movable terminal. On the other hand, when the signal sQ is at a high level, it is switched to the B side, and the movable terminals of the husband and wife are connected to (141) to (1) of the shift register 04.
4n) n-stage outputs are obtained.

The movable terminals of the switch circuits (171) to (17r+) are
Resistor (IEh) as a tap coefficient setting element ~ (
18n) terminals (191) of the resistance block θ
(19n). Terminals (191) to (19n)
are connected to the terminal - through resistors (181) to (18n)'fr. Therefore, the switch circuit (171) ~
The signals obtained at the movable terminals of (17n) are connected to the respective resistors (
181) to 0sn), and the sum signal is obtained at the terminal body).

The addition signal obtained at terminal (1) is supplied to Sanzor hold circuits (211) and (212).

Further, the signal sQ obtained at the Q output terminal of the flip-flop aO is supplied to the mono multivibrator (221) as a trigger signal. This mono multivi break (
22+) is triggered by the falling edge of the signal SQ, and an A pulse signal P1 as shown in FIG. 4G is obtained as its output.

Then, a pulse signal '4' P + delayed by a predetermined time as shown in FIG. ) is supplied as sampling (i).

On the other hand, a signal S; obtained from six outputs and one output of the flip-flop θυ is supplied to the mono multivibrator (222) as a trigger signal. This mono-multivibrator (222) is triggered by the falling edge of the 8-bit signal, and a pulse signal P2 as shown in FIG. 4I is obtained as its output.

Then, this pulse signal P2 is passed through a delay line (232) to obtain a pulse signal P2 delayed by a predetermined time as shown in FIG.
) as a sampling signal.

In addition, sample hold circuits (211) and (212)
The outputs of are passed through low-pass filters (2h) and (242
) to the output terminals (251) and (252).

This example is constructed as described above, and when the signal SQ (shown in FIG. 4E) from the Q output terminal of flip-flop 0→ is at a low level, the movable terminals of switch circuits (17+) to (17n) are set to A. When connected to the fixed contacts on the side, the movable terminals of the switch circuits (171) to (1711) provide n-stage outputs (lh) to (13n) of the shift register Q, and A signal is obtained by adding these outputs through the resistors (181) to (1sn) at the terminal (a) at the time of the bronze 20, and this added signal is supplied to the sample and hold circuits (211) and (212). Ru. At this time,
A transversal filter is configured by the shift register α and the resistance block α. At this time, the sampling signal P1 is supplied to the sample and hold circuit (2h) as shown in FIG. 4H, and this addition signal is sampled and held (see FIG. 4). Therefore, the configuration including this sample and hold circuit (211) has the same function as the roll-off filter (3) in FIG. 1, and the output terminal (251) is connected to the roll-off filter (3) in FIG. The same output as the output can be obtained.

On the other hand, Flip Flora fQ! The signal sQ from the Q output terminal of No. 3 is high level, and the switch circuits (171) to (17n
) when the movable terminals are connected to the fixed terminals on the B side, respectively,
The movable terminals of switch circuits (171) to ('i'yn) are connected to (141) to (i'an) of shift register 04, respectively.
) are obtained, and those outputs are connected to the terminals of resistors (181) to (18n) at the resistor block cI.
A boosted signal is obtained through the circuit, and this added signal is supplied to sample and hold circuits (2h) and (212). At this time, a transformer signal filter is constructed by the shift register 0→ and the resistor block θ barrel. At this time, a sampling signal P2 as shown in FIG. 4J is supplied to the Sanzor hold circuit (212), and this addition signal is sampled and held (see FIG. 4).

Therefore, the configuration including this sample and hold circuit (212) has the same function as the roll-off filter (4) in FIG. 1, and the output terminal (252) is connected to the roll-off filter (4) in FIG. The same output as the output can be obtained.

As described above, according to this example, a filter having the same function as the two roll-off filters (3) and (4) in FIG. 1 is constructed using one resistor block Q frame. Therefore, it can be constructed at low cost. Again for the same reason! When implementing J LSI, the number of connection pins with external resistance blocks can be reduced.

Furthermore, for the same reason, when it is placed in the resistor block 1LsI, the chip area can be reduced.

In the above-mentioned embodiment, the function of two transversal filters is shown, but the function of three or more transversal filters is also possible by using a resistor block (1→ In the above embodiment, resistors (181) to (tsn) were used as tag coefficient setting elements, but
The present invention is not limited to this, and other elements such as a capacitor may be used.

Effects of the Invention According to the present invention described above, since several devices having transversal filter functions are constructed by using an expensive tag coefficient setting element, the construction can be made relatively inexpensively. Further, according to the present invention, since the tap coefficient setting element is shared, the number of connection bins of the external tap coefficient setting element can be reduced when integrated into an LSI, compared to the case where a plurality of transversal filters are used. can. Furthermore, according to the present invention, since the tag coefficient setting element is also used, the chip area can be reduced when the tap coefficient a setting element is included in the LSI, compared to the case where a plurality of transversal filters are used. .

[Brief explanation of the drawing]

FIG. 3 is a connection diagram showing an embodiment of the present invention, and FIG. 4 is a diagram for explaining the same. Qo and (6) are output terminals, o3 and (1→ are shift registers, respectively, (171) to (17n) are switch circuits, respectively, ◇e is a resistor block, (2h) and (212)
are sample and hold circuits, (25+) and (252), respectively.
) are the respective output terminals. Figure 3 Figure 4

Claims (1)

[Claims] A delay system of two or more systems having tap groups, a multiplexer for switching each tap group of the delay system, a tap coefficient setting element connected to each output side of the multiplexer, and a tap coefficient setting element from each of the tap coefficient setting elements. A transparsal filter characterized in that it is similar to means for adding the outputs of the above, and means for separating the added output into two or more systems in association with the multiplexer.