JPS59135927A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To attain ease of circuit integration of a converter by applying the same input signal to an input terminal of the A/D converter and giving a clock having different phase to a switch means of each A/D converter so as to select an excess output ad a data output from each converter sequentially by switches. CONSTITUTION:A one-bit A/D converter AD2 is provided with A/D converters AD11-AD13 connected in parallel and the same input signal is applied to input terminals VIN1-VIN13 of the converters AD11-AD13. Pairs of switches S21, S22, S23, S24 and S25, S26 are connected to each output of the converters AD11- AD13, the switches S21, S23, S25 are connected to an output terminal V02 and the switches S22, S24, S26 are connected to an output terminal D02. The switch means at the inside of the converters AD11-AD13 and the switches S21-S26 at the output side are received respectively with clocks CP1, CP2 and CP3 having different phase from clock terminals and an excess output and a data output are selected sequentially by the switches S21-S26 and the circuit integration of the converter AD2 is made easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an improvement of a cascade type A/D converter.

[Prior art]

FIG. 1 shows a 1-bit A/D converter used in a conventional cascaded A/D converter. Input signal vIN is input terminal 1
When added to the sample and hold circuit (S/H
The held voltage vH (=vlN) and the reference voltage V/2 are compared in a comparator circuit 5. When vH<vR/2, the output vOD of the comparator circuit 3 becomes a low level surface and closes the switch S1.
82 is opened and the operational amplifier 4 outputs V: '2 VH:
2 Output MIN. When vu > VR/2 A Output V of comparator circuit 3. D becomes No Irepel (ro),
Switch S1 is opened, 82 is closed, and from operational amplifier 4 V
Outputs OA=2VH-%""2VIN-VR. Second
The figure shows the remainder output voA from the operational amplifier 4 and the input signal VI.
This diagram illustrates the relationship with N. That is, the input signal V
After IN is compared with the reference voltage VH/2 and 1-bit conversion is performed, the remainder 1 from the comparison voltage is output.

If multiple stages of A/D converters (one pit shown in Figure 1) are connected in cascade and the remainder output of the previous stage is used as the input of the latter stage, the combination of one pit output (comparison output) from each stage will be the same as that of multiple pits. A
Configure /D conversion output.

However, in the case of a 1-bit A/D converter as shown in Fig. 1, the offsets of the S/H circuit 2, comparator circuit 3, operational amplifier 4, and on-resistances of switches 81 and 82 are all caused by the A/D converter. Factors that limit the accuracy of For this reason, it has the disadvantage that good performance cannot be obtained if complicated and expensive components are used, and it is difficult to integrate into an IC.
Although the principle of the D conversion method is relatively simple, cascaded dust A/D converters have not been put into practical use until now.

〔the purpose〕

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to realize a cascade type A/D converter with a simple configuration and good performance (which can be easily integrated into an IC).

〔overview〕

In order to achieve the above object, the first gist of the present invention is to provide a first capacitor, a second capacitor connected in relation to one end of the first capacitor, and a second capacitor connected to one end of the first capacitor. An inverting amplifier whose input terminal is connected to the other end thereof, and switch means for switching the connection state of the circuit using a switch, the switch means charging a second capacitor with a voltage corresponding to the input signal to provide a reference voltage. After charging a first capacitor with a voltage corresponding to the voltage and comparing the input signal and the reference voltage, the holding voltages of the first and second capacitors are determined in accordance with the comparison result. a 1-bit A/D connected to form a circuit configuration that performs arithmetic operations regarding the input signal and the reference voltage using the 1-bit A/D;
Connect multiple converters in parallel to transmit the same human signal to each A/
In addition to the input of the D converter, the phases of the clocks applied to each of the A/D converters are shifted from each other so that the residual output and data output from each of the A/D converters are selected and output in order by the switch. The present invention relates to a multiple parallel type 1-bit A/D converter characterized in that it is configured as follows.

A second aspect of the present invention is to provide a first capacitor and a second capacitor connected to one end of the first capacitor.
a capacitor, an inverting amplifier whose input terminal is connected to the other end of the second capacitor, and switch means for switching the connection state of the circuit using a switch, the switch means having a voltage corresponding to an input signal. After charging the second capacitor with a voltage corresponding to the reference voltage and comparing the input signal with the reference voltage, the first and second capacitors are charged with a voltage corresponding to the reference voltage. 2
A plurality of 1-bit A/D converters are connected in parallel to form a circuit configuration that performs arithmetic operations regarding the input signal and the reference voltage using the holding voltage of the capacitor. In addition to the input of the D converter, the phases of the clocks applied to each of the A/D converters are shifted from each other, and the residual output and data output from each of the A/D converters are selected and output in order by a switch. A/D converters are connected in series in multiple stages, and the residual output from each stage is used as the input signal for the next stage, and the combination of 1-bit data output from each stage is used as the output. The invention resides in a multi-bit A/D converter characterized by the following.

[Explanation of Examples]

The present invention will be explained below using the drawings.

FIG. 5 is an electric circuit diagram showing a basic circuit constituting an embodiment of the present invention, which is a 1-bit A/D converter, and will be explained prior to the embodiment in order to facilitate understanding of the embodiment. 11
is an input terminal to which the analog input signal vIN1 is applied, 8
11 is a switch whose one end is connected to this input terminal 11, C1 is a first capacitor whose one end is connected to the other end of this switch 811, S12 is a switch whose one end is connected to the other end of this capacitor C1, and whose other end is connected to is a switch connected to common, S13 is a switch whose one end is connected to the other end of the switch 811 and the other end is connected to the terminal 12 to which the reference voltage vR/2 is applied, and C2 is a switch whose one end is connected to the other end of the switch S11. The second capacitor 15 connected is an inverting amplifier whose other end is connected to its input terminal, and for example, a CMO8 inverter can be used.

814 is a switch connected to the output terminal of the inverting amplifier 13 and the input terminal; R1 and R2 are the switches connected to the inverting amplifier 1;
a resistor of equal value connected to the output terminal of No. 5 to divide the output vo; S16 is a switch connected to the connection point of the resistors R1 and R2 and the other end of the capacitor c1;
815 is a switch connected to the connection point between the resistors R1 and R2 and one end of the capacitor c1.

14 is a switch S11. Clock C that controls S14
Clock input terminal to which P1 is applied, 15 is switch s
12 is a clock input terminal to which a clock CP2 for controlling 813 is applied; 16 is a clock input terminal to which a clock cps is applied; 17 uses this clock CP3 as its clock input; and its D input is the comparison output from the inverting amplifier 15. D-type slip-flop (hereinafter referred to as F-F
18 is an AND circuit which receives the inverted output of this D-type FF and the clock CP5 and applies the output to the switch 815, and 19 has the non-inverted output of this D-type FF and the clock CP3 as inputs. Switch output to S16
This is an AND circuit that adds and adds 20 is an output terminal for sending the output from the inverting amplifier to the outside.

The switches S11 to S16, the D-type F-F17, and the AND circuits 18 and 19 constitute switching means for switching the connection state of the A/D conversion circuit.

Next, the operation of this circuit will be explained. The entire circuit is driven by five-phase black circuits CP1 to CP41 shown in FIG.

In the first period T1 when the clock CP1 is H, the switches 811 and 814 are closed, and the other switches are open. When the switch 814 is closed, the input and output terminals of the inverting amplifier 15 have a constant value voFF (offset voltage of an operational amplifier, threshold voltage of an inverter, etc.), and therefore the capacitor C2 has a voltage between the terminals vIN1- ■OFF
will be charged.

In the second section T2 when the clock CP2 is H, only the switches 812 and 813 are closed. At this time, cl is charged to the reference voltage vR/2, and the inverting amplifier 130 input voltage Vx
Hato becomes. Since the switch 814 is open, the inverting amplifier 13 acts as a comparator and the input voltage VX is
If it is higher, the comparison output of the inverting amplifier 15 will be higher, and vice versa.
As a result, an A/D conversion output of 1 bit is obtained.

In the third period T5 when the clock CP3 becomes H, only one of the switches S15 and S16 is closed. The comparison output from the operational amplifier 13 in the interval T2 is transferred to the output side of the D-type F-F17 at the timing of the rise of the clock CP3, and when the comparison output is L, S15 is closed and when the comparison output is H. S16 closes, and in both cases, Vx = V□pp, resulting in equilibrium.

That is, when the comparison output is L, Therefore, the output vO4 of the inverting amplifier 13 is vol:2vIN1 becomes. On the other hand, when the comparison output is H, similarly, vol:2vIN1-vR The remainder output is obtained.

As is clear from the relationship shown above, by adopting such a configuration, it is possible in principle to eliminate the influence of offset on the A/D conversion output and the remainder output.

Furthermore, since the system uses a canopy, no current flows in a balanced state, so there is no error caused by the on-resistance of the switch. Furthermore, the configuration is simple, as the S/H circuit, comparison circuit, arithmetic operation circuit, etc. are implemented with one inverting amplifier. Furthermore, the main parts of the circuit are only an analog switch, an innocouple, a small capacitor, and a resistor with the same resistance value, and no particularly high-performance elements are required, making it suitable for IC implementation.

In the circuit shown in FIG. 5, when the capacitor C2 is charged by the input signal, if the signal source impedance is high, the charging time becomes long. In order to improve this point, a buffer 7B (not shown) may be inserted at point P in FIG. 3 and its output may be applied to the capacitor C2. In this case, the offset of buffer B can be considered similar to the offset of inverting amplifier 13, and the advantage of offset cancellation can remain as is.

Figure 5 is an electrical circuit diagram showing an embodiment of the present invention, and is a multiple parallel 1-bit A/D converter in which three of the basic circuits shown in Figure 3 are connected in differential series to increase the sample rate. It is. In the figure, AD11 to AD15 are AD+ of the A/D converter in Figure 6.
The same signal human power vIN2 and the same reference voltage vR/2 are applied. Clock CPI~CP3
(see FIG. 4) are added to AD11 to AD13 with their phases shifted from each other as shown in FIG.

821, 825. S25 is a switch for selecting the remainder output VO2 to be added to the feedback resistor R1 from among the remainder outputs AD11 to AD13, and is driven by the clocks CPU, CPi, and CF2 shown in parentheses, respectively. S2
'2. S24.826 is 1 bit data output DO2
This is a switch for selecting the 1-bit data output from AD11 to AD15, and the clock CP2. Driven by CPU and CP1.

The operation of the A/D converter having such a configuration will be explained below. At the timing of clock CP1, data output DO2 is given from AD15, and the remainder output V. □・ is given from AD12゛. - At the timing of clock CP2, data output DO2 is from ADjl, and remainder output VO2 is from AD.
Given from 13. At the timing of clock CP3, data output DO2 is from AD12, and remainder output vo2 is from A.
Given by DH. In other words, with the circuit shown in Figure 3, a conversion output can be obtained only once every six clocks, but with the above configuration, an output can be obtained every thick lock, and the A/D converter sample・You can increase your rate.

Furthermore, since the feedback resistors R1 and R2 are commonly used by AD11 to AD13, there is an advantage that there is no variation in errors for each conversion.

The other advantages of the A/D converter shown in FIG. 3 remain unchanged in this embodiment.

FIG. 6 shows a second embodiment of the present invention, in which four A/D converters shown in FIG. 5 are connected in series to form a 4-bit A/D converter. That is, AD21 to AD2
4 is the 1-bit A/D converter AD2 in FIG.
Signal input as input VIN21 of /D converter AD21 -
vIN5 is added, and the residual output of the A/D converter of each stage becomes the signal input of the next stage, enabling high-speed traveling wave conversion. 41 to 50 are D-type F-Fs for holding and transferring A/D conversion outputs from each stage, and A/D converter AD21.
The 1-bit A/D conversion output from
CF2. D at the timing of CF2 (see Figure 4)
The data is held in the D-type F-R 41 and sequentially transferred to the D-type 1 F-R 42, 44, and 47 by each of the clocks. LA/D converter AD22 in another stage. AD23. The A/D conversion output from AD24 is also transferred in the same way, and finally the D
Each output D5. from F-R47, 4849, 50. D
2. 4-bit as Dl, DO.

A/D conversion output can be obtained.

By adopting such a configuration, in addition to the same advantages as in the case of FIG. 5, it is possible to increase the number of A/D conversion outputs, that is, the accuracy.

In the above embodiment, a case is shown in which four stages of A/D converters are used; however, the present invention is not limited to this, and it is also possible to further increase the number of stages.

In addition, the accuracy of A/D conversion in this case is determined only by the matching of the two resistors (R1 and R2 in Figure 5) for each stage, and there is no need to match each stage to another, so it is easy to increase the accuracy. It is.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a cascaded ff1 A/D converter with a simple configuration, good performance, and easy integration into an IC.

[Brief explanation of drawings]

FIG. 1 is an electrical circuit diagram showing a conventional cascade type A/D converter;
Figure 2 is a time diagram for explaining the operation of the circuit in Figure 1.
3 is an electric circuit diagram showing a basic circuit constituting an embodiment of the present invention; FIG. 4 is a time chart for explaining the operation of the circuit in FIG. 3; and FIG. FIG. 6 is an electrical circuit diagram showing a second embodiment of the present invention. 13... Inverting amplifier, ADD, AD11 to ADi3
DE921~AD24・1 pit A/D converter, C4, C
2... Capacitor, 811-S16. 821-S
26...-Switch, vIN, vIN1 to VIN51
vINF1~VIN13I■IN2+-■IN24"'
Input signal ~Vlt/2''・base single voltage, CP+ ~
cps...Clock, v02゜■021~■o23
°°゛Remainder output Do21Do21~Do24IDo~
D3...Data output.躬 l 2 阿 3 shout 5 / 1 η 41 eyes, r, t,, 5: /; 1

Claims (4)

[Claims] (1) a first capacitor; a second capacitor connected in relation to one end of the first capacitor; and an inverting amplifier whose input terminal is connected to the other end of the second capacitor; switch means for switching the connection state of the circuit using a switch, the switch means charging the second capacitor with a voltage corresponding to the input signal and charging the first capacitor with a voltage corresponding to the reference voltage; A circuit configuration that, after comparing the input signal and the reference voltage, performs an arithmetic operation regarding the input signal and the reference voltage using the holding voltages of the first and second capacitors in accordance with the comparison result. 1 and A connected so that
A plurality of A/D converters are provided, and the same human signal is sent to each of the A/D converters.
In addition to applying clock signals to the input terminals of the converters, the clock signals whose phases are shifted from each other are applied to the switch means of each of the h/D converters, and the residual output and data output from each of the A/D converters are sequentially switched by the switches. 1. A multiple parallel type 1-bit human/D converter, characterized in that it selects and obtains the data. (2) The A/D converter according to claim 1, wherein the switch and the inverting amplifier are composed of CMO8. (3) A first capacitor, a second capacitor connected in relation to one end of the first capacitor, an inverting amplifier whose input terminal is connected to the other end of the second capacitor, and the above circuit. switch means for switching the connection state using a switch, the switch means charging the second capacitor with a voltage corresponding to the input signal and charging the first capacitor with a voltage corresponding to the reference voltage to switch the input signal. and the reference voltage, and then performs an arithmetic operation regarding the input signal and the reference voltage using the holding voltages of the first and second capacitors in accordance with the comparison result. 1-bit A/D to connect
A plurality of converters are provided, and the same human input signal is applied to the input terminal of each of the A/D converters, and clock signals whose phases are shifted from each other are applied to the switch means of each of the A/D converters. A plurality of parallel 1-pit A/D converters are connected in cascade so that the residual output and data output from the D converter are selected in order by switches, and the residual output of each stage is used as the input of the next stage. A multi-bit A/D converter characterized in that the output is a combination of 1-bit data outputs from each stage. (4) The A/D converter according to claim 3, wherein the switch and the inverting amplifier are composed of CMO8.