JPS6081664A - Microcomputer system - Google Patents

Abstract

PURPOSE:To prevent malfunction due to the miss of a protection error by writing the protection error periodically and checking the detection of the protec- tion error to monitor a protecting circuit. CONSTITUTION:At data writing to an RAM2, a memory writing signal M/W of logic ''1'' is inputted from a CPU1 to an AND gate 42 through a signal line 13 to check a protection area selecting circuit 41. If the area is a write disabled area, the signal M/W is turned to logic ''0'' and a write enable (WE) signal indicating write enable state is not generated from the gate 42 because an input condition is not formed in the gate 42. However, the input condition is formed in an AND gate 43, an interruption signal is generated on the output side and a protection error is detected. The interruption signal is inputted to the CPU1 and whether the protecting circuit is in checking or not is discriminated. If the discriminated result is NO, the memory protecting circuit 4 is decided as abnormal status because the interruption signal is generated in spite of no checking.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microcomputer system 1, and more particularly to a failure detection technique thereof.

Prior Art and Its Problems In microcomputer systems, random access memory (rRAMJ) is used to prevent important information from being rewritten.
A protection circuit may be provided.

However, simply by providing a memory and a protection circuit, if the memory and protection circuit fail, the system cannot detect it. Therefore, if a protect error occurs after the memory or protect circuit fails, the abnormality cannot be detected, and the system mistakenly assumes that the memory protect circuit is normal and operates, leading to a double failure. There was a problem with the transition.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and
It is an object of the present invention to provide a microcomputer system in which the function of a protect circuit is periodically inspected to prevent malfunction due to detection of a protect error and to prevent transition to a double failure.

Structure of the Present Invention In order to achieve the above object, the present invention provides a microcomputer system having a memory and a protect circuit that prevents rewriting of information stored in the memory, in which data that would cause a protect error is previously destroyed. The present invention is characterized in that the normality or abnormality of the memory and the protection circuit is monitored by periodically writing a protection error and confirming that the protection error is detected.

Embodiment FIG. 1 is a block diagram of a microcomputer system according to the present invention. In the figure, 1 is a microcomputer (hereinafter referred to as rcPUJ), 2 is a RAM, and 3 is a read-only memory (hereinafter referred to as rROMJ). The RAM 2 divides addresses into several areas, and allows protection to be set/cancelled for each area.

4 is a memory and a protect circuit that protects the RAM 2 and prevents the information stored in the area from being rewritten.

The memory and protect circuit 4 includes a protect instruction latch circuit 40, a protect area selection circuit 41, AND gates 42 and 43, an inverter 44, and the like. The protection instruction latch circuit 40 is RAM2.
This is a circuit that stores protection setting/cancellation for each area, and its contents can be changed by receiving data from the CPUI. The protect area selection circuit 41 also includes a protect instruction latch circuit 40.
A protect area is selected based on a protect instruction signal given by the CPU and an address signal given from the CPU, and if the area is writable, a logic "1" is output.

5 is a transformer-coupled AC amplifier circuit, 6 is a rectifier circuit, 7 is a relay, 71 is a contact thereof, and 8 is a power source. 9 is an address bus, IO is a data bus, and 11 is an interrupt signal line.

Next, the operation will be explained with reference to the flowcharts in FIG. 2(a) and υ(+)). First, according to the software, normal process processing and failure checking of the memory and protection circuit 4 are periodically and alternately performed at fixed time intervals. Then, when the normal process is completed, as shown in Figure 3 (
As shown in a), the software is checking the memory and protection circuit 4. Data that will cause a protect error is preset in the CPUI, and when the software is checking the memory and protect circuit 4,
This data is periodically written to the protect instruction latch circuit 40 through the data bus 10. The protect area selection circuit 41 selects the protect area of the RAM 2 based on the address signal applied from the CPUI via the address bus 9 and the protect instruction signal applied from the protect instruction launch circuit 40. Then, if the selected area is writeable (H), a logic "1" is output to the signal line 12, and is input to the anchor 43 through the AND gate 42 and the input/hater 44.

On the other hand, when writing data to RAM2, CP
A logic rlJ memory/write signal (hereinafter referred to as rM/W signal) is input from TJl to AND gate 42 through signal line 13, and the protected area selection circuit 41 is checked. Here, if the area selected by the protect area selection circuit 42 is writable, the logic rlJ signal is output from the protect area selection circuit 42 to the signal line 12 as described above. is set, and a WE double signal is input from the AND gate 42 through the signal line 14, which means that writing is possible in the RAM 2. Note that the logic rlJ(7) M/W signal is also input to the AND gate 43, but since the input 44 is connected before the AND gate 43, the output of the AND gate 43 is logic "0". It is.

However, if writing is not possible, signal line 1 is sent from CPtJl.
The M/W signal applied to the AND gate 42 through the AND gate 3 becomes logic "0", and the input condition is not correct on the ant gate 42 side, so the WE@ signal is not generated.
In step 3, the input conditions are checked, an interrupt signal is generated on the output side of the ant gate 43, and a protect error is detected. This interrupt signal is input to the CPUI through the signal line 11, and as shown in flowchart 1 of FIG. 3(b), it is determined whether or not the memory and protection circuits are being checked. Software can determine whether or not the memory and protection circuits are being checked. When the result is rYESJ, the memory and protection circuit check processing is canceled and the process moves to the next process processing software.

On the other hand, if the result of the above judgment is "NO", since the interrupt signal was generated even though the memory and protection circuit were not being checked, it is judged that the memory and protection circuit 4 are abnormal, and a stop command is issued. Let it run.

As mentioned above, if the memory and protection circuit 4 are normal, normal process processing and memory and protection circuit check processing are performed periodically at fixed time intervals, and an interrupt is generated every time the memory and protection circuit check processing is performed. A signal is generated. Therefore, the output of the memory and protection circuit 4 becomes a pulse train, which is amplified by the transformer-coupled AC amplifier circuit 5.
The AC signal is input to the rectifier circuit 6, and a rectified output is obtained from the rectifier circuit 6. Therefore, the relay 7 is closed, and the contact 71 inserted and connected in series to the power supply 8 is closed, and the CPUI receives f# and the connection. power is supplied.

On the other hand, if a protect error cannot be detected because the memory or protect circuit 4 has failed, no interrupt signal is generated and the output of the memory or protect circuit 4 does not become a pulse train, so the output of the transformer-coupled amplifier 5 is A constant DC level or no output. Further, even when a stop command is executed according to software, the output of the memory and protection circuit 4 does not become a pulse train. Therefore, in these cases, a rectified wave output cannot be obtained from the rectifier circuit 6 and the relay 7 falls, so that the contact 7
1 opens, the power supply to the CPUI is cut off, and the
The UI stops without performing any abnormal operations.

Effects of the Invention As stated in the second series, the present invention provides a method for setting data that will cause a protect error in advance in a microcomputer system that has a memory and a protect circuit that prevents the rewriting of information stored in the memory. and write protection errors periodically.

By confirming that this protect error is detected, the normality or abnormality of the memory and the protect circuit is monitored.The function of the memory and the protect circuit is periodically inspected to detect the protect error. It is possible to provide a microcomputer system that can prevent malfunctions due to oversight and prevent transition to a double failure.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of the microcomputer system according to the present invention, and FIGS. 2(a) and (b) are flowcharts of the microcomputer system according to the present invention. l...φ Microcomputer (CPU) 2...Random, access, memory (RAM) 4...Memory, protect circuit 40...Latch circuit for protection instruction 41・φ Life protection area selection circuit 2nd diagram 1 included lf, feed〉 (0)

Claims (1)

[Claims] (1) A memory that prevents the information stored in the memory from being rewritten;
In a microcomputer system having a protect circuit, by setting data that will cause a protect error in advance, generating a protect error periodically, and confirming that this protect error is detected, the memory protect circuit can be protected. A microcomputer system that monitors normality and abnormality.