JPS6080896A - メモリ制御回路 - Google Patents
メモリ制御回路Info
- Publication number
- JPS6080896A JPS6080896A JP58189461A JP18946183A JPS6080896A JP S6080896 A JPS6080896 A JP S6080896A JP 58189461 A JP58189461 A JP 58189461A JP 18946183 A JP18946183 A JP 18946183A JP S6080896 A JPS6080896 A JP S6080896A
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- cpu
- signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims description 41
- 230000002457 bidirectional effect Effects 0.000 claims description 21
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100328887 Caenorhabditis elegans col-34 gene Proteins 0.000 description 1
- 102100031584 Cell division cycle-associated 7-like protein Human genes 0.000 description 1
- 101000777638 Homo sapiens Cell division cycle-associated 7-like protein Proteins 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
- Controls And Circuits For Display Device (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58189461A JPS6080896A (ja) | 1983-10-11 | 1983-10-11 | メモリ制御回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58189461A JPS6080896A (ja) | 1983-10-11 | 1983-10-11 | メモリ制御回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6080896A true JPS6080896A (ja) | 1985-05-08 |
| JPH0535434B2 JPH0535434B2 (enrdf_load_stackoverflow) | 1993-05-26 |
Family
ID=16241651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58189461A Granted JPS6080896A (ja) | 1983-10-11 | 1983-10-11 | メモリ制御回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6080896A (enrdf_load_stackoverflow) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843035A (ja) * | 1981-09-08 | 1983-03-12 | Matsushita Electric Ind Co Ltd | 記憶表示装置 |
-
1983
- 1983-10-11 JP JP58189461A patent/JPS6080896A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5843035A (ja) * | 1981-09-08 | 1983-03-12 | Matsushita Electric Ind Co Ltd | 記憶表示装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0535434B2 (enrdf_load_stackoverflow) | 1993-05-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4644502A (en) | Semiconductor memory device typically used as a video ram | |
| US4961171A (en) | Read/write memory having an on-chip input data register | |
| US4807189A (en) | Read/write memory having a multiple column select mode | |
| US5195056A (en) | Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits | |
| US4688197A (en) | Control of data access to memory for improved video system | |
| US4104624A (en) | Microprocessor controlled CRT display system | |
| US5099331A (en) | Apparatus for overlaying a displayed image with a second image | |
| US5218274A (en) | Flat panel display controller using dual-port memory | |
| US4075620A (en) | Video display system | |
| GB2149157A (en) | High-speed frame buffer refresh apparatus and method | |
| JPS598193A (ja) | ランダム・アクセス・メモリ | |
| JPH0141994B2 (enrdf_load_stackoverflow) | ||
| US4720819A (en) | Method and apparatus for clearing the memory of a video computer | |
| US5438376A (en) | Image processing apparatus and image reception apparatus using the same | |
| US6734863B1 (en) | Display controller for display apparatus | |
| KR100273111B1 (ko) | 그래픽 메모리 장치의 리프레쉬 제어방법 및 회로 | |
| JPS6080896A (ja) | メモリ制御回路 | |
| KR950704768A (ko) | 고속프레임버퍼 시스템에서 파이프라인된 판독 기록동작(pipelined read write operations in a high speed frame buffer system) | |
| EP0613115B1 (en) | Display data write control device | |
| JP2507361B2 (ja) | 画像情報処理装置 | |
| JPS61190387A (ja) | フレーム・バツフア・メモリ用制御器 | |
| JPS6024586A (ja) | 表示デ−タの処理回路 | |
| JPS63250689A (ja) | ラスタ走査表示システム | |
| JPS6122391A (ja) | 表示装置の複写制御方式 | |
| JP3694622B2 (ja) | 画像表示データの生成方法 |