JPS6080252A - Gate array system mos ic device - Google Patents

Abstract

PURPOSE:To enhance the resistance to radiations by blocking MOS inversion by prevention of the accumulation of positive residual space charges under an insulation film by a method wherein in the tile device a conductor layer connected to the minimum potential by being positioned in an interlayer insulation film is provided under a wiring layer of a high potential. CONSTITUTION:By sandwiching P<+> type buried regions 8, N<+> type source and drain regions 3 are formed therebetween, and a gate electrode 4 is provided on a channel between the latter regions via gate insulation film into the MOS-IC of gate array system. A thick interlayer insulation film 11 is provided on the region 8, and an Al wiring 10 on which a high potential is impressed is formed thereon. At this time, the conductor 9 is buried in the insulation film 11 by being positioned under the wiring 10, and is connected to the minimum potential. Such a manner enables the prevention of the increase in leakage currents for MOS inversion. The arrangement of these basic cells enables the IC device suitable for mounting, etc. in an artificial satellite to be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a gate array type MO8 integrated circuit device, and particularly to a radiation-resistant gate array type MO8 integrated circuit device.

(2) Description of the Prior Art The MOS transistor of a conventional general gate array type MO8 integrated circuit device has the structure shown in FIG. The figure shows a sectional view and a plan view.

FIG. 2 is an enlarged view of the field arrangement membrane portion.

To briefly explain the case of an N-channel MO8) transistor, an N+ region 3 equivalent to the drain and source is diffused inside the pattern 2 of the field oxide region 5 on the P-type substrate 1, and a gate 4 made of aluminum or polysilicon is formed. It has a structure in which the region 1 and the gate 40 are insulated by a thin gate oxide film 6. The portion other than the MO8 transistor region is covered with a thick field oxide film 5 to increase the threshold voltage under the field oxide film. Further, a P+ region 8 called a guard ring is buried under the field oxide film to prevent MO8 inversion of the P- region 7' directly below the shift due to the electric field generated by the wiring pattern 7. M
O8 reaction transfer U3 low value voltage is further increased. If MO8 is inverted in the part directly below 7, current leakage occurs between adjacent transistors, and if there is a ground wiring (e.g. sub-contact) in the adjacent part, leakage current between the power supply and ground increases. becomes. In a normal design, the inversion threshold voltage directly below the expansion point 7 is designed to be 10 to 30 V, so inversion does not occur under normal usage environments.

In recent years, space exploration and the development of nuclear power facilities have progressed, and the demand for radiation-resistant devices has increased. In the space environment, semiconductor devices are exposed to radiation that causes ionization, such as small amounts of heavy ions and large amounts of electron beams. In the environment of a nuclear facility, semiconductor devices are exposed to many types of radiation.

The general damage to MOS transistors exposed to these radiations is explained as follows.

Tsumu JMO8) When radiation such as electron beams or X-rays that cause ionization is incident on a transistor, electron-hole pairs are generated in the oxide film. Since electrons are easy to move, they drift toward the anode, but holes are difficult to move, so they remain in the oxide film near the silicon-oxide film interface as a positive residual space 1, a charge. As the positive space charge increases, the electric field decreases, so the accumulation of charges stops when the electric field becomes zero. Therefore, the accumulation of positive space charges depends on the potential of the conductor on the oxide film. The accumulation of this positive residual space charge is considered to be damaging in that it lowers the gate threshold voltage of the N-channel MOS transistor. Further, when a high voltage of about VDD is applied to the wiring pattern 7 in FIG. 2, positive residual space charges also accumulate in the portion 8 in the field oxide film. This lowers the threshold voltage of the field oxide crotch in the same way as lowering the threshold voltage of the siggate.
Causes damage such as increased leakage current.

The amount of residual space charge explained above depends on the total amount of radiation absorbed by the MO8 device, and in the space environment it is 10' ra
Radiation resistance of the order of d(,S+i) is required.

(3) Detailed Description of the Invention The present invention relates to MO8 integrated circuit devices for use in satellites, etc. that require radiation resistance, and that are manufactured in a wide variety of products in small quantities or with short delivery times. By arranging a conductor with the same potential as the lowest potential of the field oxide film, it is possible to prevent the accumulation of positive residual space charge under the field oxide film, making it difficult for MO8 inversion to occur. An MO8 integrated circuit device is provided.

(4) Structure of the Invention The present invention provides a semiconductor integrated circuit device in which a conductor connected to the lowest potential of the MO8 transistor is placed around a MOS transistor in a wiring layer with a high potential, and a conductor connected to This is a gate array type MO8 integrated circuit device that can improve radiation resistance by arranging it in a gate array.

(5) Example station, Akira Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows a sectional view of this embodiment, and FIG. 4 shows a plan view. In this embodiment, polysilicon 9, which is the same as the gate, is placed around the N-channel transistor shown in FIG. In FIG. 3, 11 is an interlayer insulating film, and 10 is aluminum for wiring. The transistor bears within the dotted line 14 in FIG. 4 are arranged as basic cells. Polysilicon 9 is connected to the lowest potential of the semiconductor device from any position on the layout. Polysilicon is arranged like this, and aluminum wiring 1
Even if 0 is laid out on top of the field oxide,
Since the electric field does not reach the field oxide film, no accumulation of positive residual space charges occurs and no MOfS inversion occurs.

But the third. Although the example shown in FIG. 4 has the advantage of being able to configure the circuit with a single layer of aluminum wiring, it is not possible to increase the degree of integration because it is necessary to provide a margin between polysilicon layers. An improved version of this is the embodiment shown in FIG. If 2ffi or more of aluminum can be used in the process, an aluminum layer 13 made of the same aluminum as the first wiring aluminum in the lowest layer is arranged around the N-channel transistor and connected to the lowest potential of the semiconductor device.

From the source and drain of the N-channel transistor,
If necessary, wire with the second aluminum through the sulfonyl. Further, the aluminum 13 is also used as the lowest potential power line. This makes it possible to construct a circuit with even higher degree of integration. Furthermore, since it is possible to cover the entire field oxide film region on the P semiconductor substrate without reducing the degree of integration, a high radiation resistance purity can be obtained.

In the above example, the conductor polysilicon and aluminum are
Although these conductors are laid out around the OS transistors, they do not need to be limited to polysilicon or aluminum; any type of conductor can be used as long as they are used in the semiconductor integrated circuit device. do not have.

In addition, if it is difficult to connect to the lowest type 5, even if it is connected to a voltage slightly higher than the lowest potential, the effect will be less, but higher radiation resistance can be obtained than if there is no conductor at all.

Although only one type of basic cell configuration is described,
If necessary, an integrated circuit is constructed from a complex of several S basic cells. An example of the structure of the integrated circuit is shown in FIG. Here, basic cells 14 for internal circuit configuration are arranged periodically, and basic cells 15 for input/output circuit are arranged in a matrix to form an integrated circuit.

(6) Detailed Description of the Invention The present invention provides a method for reducing the positive residual under the field oxide film by arranging a conductor around the MOS transistor and connecting it to the lowest potential in the semiconductor device as described above. By arranging basic cells that prevent the accumulation of space charges and prevent an increase in leakage current due to MO8 inversion, it is possible to provide a gate array type MO8% product circuit with high radiation resistance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional MOS transistor. Second
FIG. 1 is an enlarged view of the field oxide film portion. FIG. 3 is a sectional view of a MOS transistor according to an embodiment of the present invention. FIG. 4 is a plan view of a MOS transistor according to an embodiment of the present invention. FIG. 5 is a sectional view of a MOS transistor according to another embodiment of the present invention. FIG. 6 is a plan view showing the overall configuration. In the figure, 1...P' semiconductor substrate, 2...
...Mask pattern showing the positions of the four costumes, 3...
...Drain or source N+ diffusion region, 4...
...Polysilicon gate, 5...Field oxide film, 6...Gate oxide film, 7...
Aluminum for wiring, 7'...Charge accumulation area in field oxide film, end...P+ guard ring, 9.
... Polysilicon, 10 ... Aluminum for wiring, 11 ... Interlayer insulating film, 12 ... Contact, 13 ... First aluminum, 14...
...Basic cell for internal circuit, 15...Basic cell for input/output circuit.The entire circuit is constructed by periodically arranging basic cells 14 and 15.り箭／Fig.Az fig.3 fig.4 fig.5

Claims (2)

[Claims] (1) In a semiconductor prefectural tax circuit device, a gate array type λiOS integrated circuit device characterized in that a MOS (MOS) transistor around which a conductor connected to the lowest potential is arranged is arranged as a basic cell. (2) The gate array type MO8 integrated circuit according to claim 1, wherein the conductor is a wiring in a layer below the high potential wiring layer or a gate conductor. Device.