JPS6078352A - Varying device of output pulse number - Google Patents
Varying device of output pulse numberInfo
- Publication number
- JPS6078352A JPS6078352A JP58187494A JP18749483A JPS6078352A JP S6078352 A JPS6078352 A JP S6078352A JP 58187494 A JP58187494 A JP 58187494A JP 18749483 A JP18749483 A JP 18749483A JP S6078352 A JPS6078352 A JP S6078352A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- pulse
- output
- ppr
- converts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P13/00—Indicating or recording presence, absence, or direction, of movement
- G01P13/02—Indicating direction only, e.g. by weather vane
- G01P13/04—Indicating positive or negative direction of a linear movement or clockwise or anti-clockwise direction of a rotational movement
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Control Of Electric Motors In General (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、パルスジェネレータの１回転あたりの出力パ
ルス数をそのスリット数以下で仁君に可変できる出力パ
ルス数可変装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output pulse number variable device that can freely vary the number of output pulses per revolution of a pulse generator within the number of slits.
〔背景技術」
従来サーボモータ等の回転数を検出するために用いられ
るパルスジェネレータ（以下、ＰＧと称する）は、その
１回転あたりの出力パルス数（以下、ＰＩ”Ｒと称する
）が固定されている。ところが、ＮＣ工作機等のサーボ
系の回転数フィードバックに用いられるＰＧのＰＰＲは
、ボールネジのピッチやギヤ比、又は、パルス処理部の
逓倍比などから決定きれるのが実情である。[Background Art] Conventionally, a pulse generator (hereinafter referred to as PG) used to detect the rotation speed of a servo motor, etc. has a fixed number of output pulses per revolution (hereinafter referred to as PI"R). However, the reality is that the PPR of a PG used for feedback of the rotation speed of a servo system such as an NC machine tool can be determined from the pitch and gear ratio of a ball screw, or the multiplication ratio of a pulse processing section.
そのため、各種条件にあったＰＧを提供するために、前
記Ｐ Ｐ Ｒの異なる機種を多数備えておかなければな
らないという欠点があった。Therefore, in order to provide PGs that meet various conditions, it is necessary to have a large number of different types of PPRs.
本発明は、上記欠点を解消し、ＰＧから出力される２相
パルスのＰＰＲをそのＰＧのスリット数以下の範囲で任
意に可変できる装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a device that can arbitrarily vary the PPR of a two-phase pulse output from a PG within a range equal to or less than the number of slits in the PG.
以下、図面を参照して本発明の具体的実施例を説明する
。第１図は、本発明の具体的回路図でるり、■はパルス
処理回路部、２は積分回路部、３は２相化回路部、４は
ＰＰ几設定部である。ただし、ここでは、ＰＧのスリッ
ト数を１０２４ ＜＝２１．０）として説明する。従来
であれば、スリット数イコールＰＰＲである。Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a specific circuit diagram of the present invention. 2 is a pulse processing circuit section, 2 is an integration circuit section, 3 is a two-phase circuit section, and 4 is a PP setting section. However, here, the description will be made assuming that the number of slits in the PG is 1024 <=21.0). Conventionally, the number of slits equals PPR.
さて、パルス処理回路部１は、ＥＸＯＢ、１−ａ、イン
バータ １−ｂ、ＦＵＬＬ ＡＤＤＥＲ１−Ｃ，Ｄフリ
ップフロップ １．−ｄからなっており、ＰＧの２相パ
ルス出力Ａｉ 、Ｂｉを２進数データΣ１、Σ０に変換
するものである。すなわち、図示した回路かられかるよ
うに、ＰＧが正転時は（Σ１、Σ０）−（０、■）、逆
転時は（Σ１、Σ０）＝（１，１）、浮止時は（Σ１、
Σ０）＝（０，０）と々るよう構成されている。Now, the pulse processing circuit section 1 includes EXOB, 1-a, inverter 1-b, FULL ADDER 1-C, D flip-flop 1. -d, which converts the two-phase pulse outputs Ai and Bi of the PG into binary data Σ1 and Σ0. That is, as can be seen from the circuit shown in the figure, when the PG rotates in the normal direction, (Σ1, Σ0) - (0, ■), when the PG rotates in the reverse direction, (Σ1, Σ0) = (1, 1), and when it is floating, (Σ1 ,
It is configured so that Σ0)=(0,0).
ＰＰＲ設定部４は、１０個のスイッチからなし、１０２
８（＝２１０−’１ ）以下の数が自由に設定できる。The PPR setting unit 4 has 10 switches, none, 102
A number of 8 (=210-'1) or less can be freely set.
積分回路部２は、パルス処理回路部１の出力Σ０のタイ
ミングにしたがって、Ｄフリップフロップ２−ｄが保持
する前回値に、ＰＰ几設定部４で設定した値を加算又は
減算する。Σ０とともに出力をれるΣ１が０′のとき加
算、１′のとき減算となる。The integrating circuit section 2 adds or subtracts the value set by the PP value setting section 4 to the previous value held by the D flip-flop 2-d in accordance with the timing of the output Σ0 of the pulse processing circuit section 1. When Σ1, which is output together with Σ0, is 0', addition is performed, and when it is 1', it is subtraction.
すなわち、Ｄフリップフロップの出力Ｂ１〜Ｂ１０がＦ
ＵＬＬ ＡＤＤＥＲ２−Ｃに入力されるので、アキュム
レータとして機能するのである。That is, the outputs B1 to B10 of the D flip-flops are F
Since it is input to ULL ADDER2-C, it functions as an accumulator.
なお、Ｂ１−Ｂ１０ の加減等によって生ずる桁必ふれ
（オーバーフロー又はアンダーフロー）は、ηｘ−１、
ＢＸに現われる。Incidentally, the digit deviation (overflow or underflow) caused by the addition or subtraction of B1-B10 is calculated by ηx-1,
Appears on BX.
２相化回路部３は、２進数データＢｘ−１、ＢＸを２相
出力に変換する。The two-phase circuit section 3 converts the binary data Bx-1 and BX into two-phase output.
〔動 作」
さて、ここで、要求出力ＰＰＲを５００とし、すなわち
５００＝ Ｉ Ｆ４ （１１） ＝ １１１１１０１０
０（２）をＰＰＲ設定部４に設定し、Ｄフリップフロッ
プ２−ｄの初期状態を仮りに、ＢＩＯ（：Ｅｌ）として
動作させた場合を第２図に示す。[Operation] Now, let us assume that the required output PPR is 500, that is, 500 = IF4 (11) = 11111010
FIG. 2 shows a case where 0(2) is set in the PPR setting section 4 and the initial state of the D flip-flop 2-d is temporarily operated as BIO(:El).
すなわち初期状ｉＢ １０ （Ｈ）の最上位２桁ＢＸＢ
ｘ−１は１′、０′で＝Ｔｈ、りＡｏ −Ｂｏは・・１
・、１′となる。In other words, the most significant two digits BXB of the initial state iB 10 (H)
x-1 is 1', 0' = Th, riAo -Bo is...1
・, 1′.
次にＰＰＲ設定部４で設定されたＩＦ４（Ｈ）を加算す
ると、ＢＸ、’ＢＸＩは・１・、・１・となりＡｏ 、
ＢＯは０′、１′となる。Next, when IF4 (H) set in the PPR setting unit 4 is added, BX, 'BXI becomes ・1・, ・1・Ao,
BO becomes 0' and 1'.
このようにして、くり返し加算したものをタイムチャー
トに示している。The time chart shows what has been repeatedly added in this way.
Ｐｉ”Ｒ＝１０２４の２相パルスＡ’ｉ、Ｂｉから変換
された２相パルスＡＯ、ＢＯはＰＰＲ５００となってい
ることがわかる。It can be seen that the two-phase pulses AO and BO converted from the two-phase pulses A'i and Bi of Pi''R=1024 have a PPR of 500.
つ丑り積分回路への入力比が５００７２１０であるので
、オーバーフロー不がそのまま５００／２１０となり１
周１０２４個のパルスに対して５００パルスが出力され
るのである。Since the input ratio to the cross-integrator circuit is 5007210, the overflow ratio becomes 500/210, which is 1
500 pulses are output for every 1024 pulses.
〔発明の効果」
以上述べたように本発明によれば、ＰＧのスリット数以
下であれば任意の数に２相パルスを変換することができ
、融通性の高い装置を提供できる。[Effects of the Invention] As described above, according to the present invention, a two-phase pulse can be converted into any number of slits as long as the number is equal to or less than the number of slits in the PG, and a highly flexible device can be provided.
なお、本発明の装置はＰＧ本体に組み込んでもよく、別
個に設けても良い。Note that the device of the present invention may be incorporated into the PG main body, or may be provided separately.
第１図は、本発明の具体的実施例、第２図は１、本発明
の詳細な説明する図である。FIG. 1 shows a specific embodiment of the present invention, and FIG. 2 shows a detailed explanation of the present invention.
Claims (1)
該パルスジェネレータの回転方向によって定まる所定の
２進数データに変換するパルス処理回路部と、 （ｂ）１回転あたりの所望の出力パルス数（ただしパル
スジェネレータのスリット数以下）を設定するＰ’ＰＲ
設定部と、（Ｃ１前記ＰＰＲ設足部で設定された定数を
、 前記２相パルスの少なくとも一方が立ち上がりまたは立
ち下がシするタイミングに同期して前記パルス処理回路
部の出方信号（２進数データ）にもとづいて加算または
減算を行う積分回路部と、（ｄｌ 前記積分回路部の上
位の桁あふれ分の２桁の２進数データを２相パルスに変
換する２相什回路とを、 備えることを特徴とする出力パルス数可変装置。[Claims] fa) a pulse processing circuit unit that converts a two-phase pulse that is the output of a pulse generator into predetermined binary data determined by the rotational direction of the pulse generator; (b) a desired output per rotation; P'PR to set the number of pulses (but not more than the number of slits of the pulse generator)
The setting section (C1) sets the constant set in the PPR setting section to the output signal (binary number) of the pulse processing circuit section in synchronization with the timing at which at least one of the two-phase pulses rises or falls. an integrator circuit section that performs addition or subtraction based on data); and a two-phase circuit that converts two-digit binary data corresponding to the upper overflow of the integrator circuit section into a two-phase pulse. An output pulse number variable device featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58187494A JPS6078352A (en) | 1983-10-05 | 1983-10-05 | Varying device of output pulse number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58187494A JPS6078352A (en) | 1983-10-05 | 1983-10-05 | Varying device of output pulse number |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6078352A true JPS6078352A (en) | 1985-05-04 |
| JPH0412406B2 JPH0412406B2 (en) | 1992-03-04 |
Family
ID=16207041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58187494A Granted JPS6078352A (en) | 1983-10-05 | 1983-10-05 | Varying device of output pulse number |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6078352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009096635A (en) * | 2007-03-30 | 2009-05-07 | Masasada Yokota | Tape cutter |
-
1983
- 1983-10-05 JP JP58187494A patent/JPS6078352A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009096635A (en) * | 2007-03-30 | 2009-05-07 | Masasada Yokota | Tape cutter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0412406B2 (en) | 1992-03-04 |
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