JPS607757A - Resin seal type semiconductor device - Google Patents
Resin seal type semiconductor deviceInfo
- Publication number
- JPS607757A JPS607757A JP58115525A JP11552583A JPS607757A JP S607757 A JPS607757 A JP S607757A JP 58115525 A JP58115525 A JP 58115525A JP 11552583 A JP11552583 A JP 11552583A JP S607757 A JPS607757 A JP S607757A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- shape
- semiconductor device
- lead frame
- metal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は樹脂封止形半導体装置に係り、特に半導体ダイ
を搭載するリードフレーム部分と、外部へ接続するリー
ドフレーム部分とが設けられ、前記半導体ダイの電極と
、前記外部へ接続するり一ドフレーム部分とが、金属細
線で接続された倒脂封止形半導体装置咳関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device, and particularly includes a lead frame portion on which a semiconductor die is mounted, and a lead frame portion connected to the outside. The frame portion connected to the outside is connected to a sealed semiconductor device connected by thin metal wires.
近年、樹脂封止形半導体装置が、保護絶縁膜、耐重材料
、封と技術等の発展に伴ない、民生用機器全中心として
広く普及しつつある。2. Description of the Related Art In recent years, resin-encapsulated semiconductor devices have become widely used in all consumer devices due to advances in protective insulating films, heavy-duty materials, sealing techniques, and the like.
樹脂封止形半導体装置は、低価格、高量産性という長所
を持つ一方で、気密封止形半導体装置に比較して特に高
温高湿下の使用環境において、配線金属の腐食が起こり
得るという重大な欠点を有している。この内子導体ダイ
の内部配線金属の腐食に対しては、保護絶縁膜等、製造
プロセスの改良を進めることにより、今後、樹脂封止形
半導体装置と言えども、十分な耐湿性を実現することは
可能と考えられる。Resin-sealed semiconductor devices have the advantages of low cost and high mass production, but compared to hermetically-sealed semiconductor devices, they have the serious problem of corrosion of wiring metal, especially in environments of high temperature and high humidity. It has some drawbacks. In order to prevent corrosion of the internal wiring metal of the inner conductor die, it will be possible to achieve sufficient moisture resistance even for resin-encapsulated semiconductor devices in the future by improving the manufacturing process such as using protective insulating films. It is considered possible.
一方、現在の樹脂封止形半導体装置においては、第1図
に示す様に、リードフレーム(図示していない)上の半
導体ダイl上の電極2は保護絶縁膜3のlll5’を除
去し、開孔部4a′t−設け、リードフレーム5と電極
2とを金属線[6により接続している。この際金属細線
6が電極2上と接触する接続部7は、第2図に示す様に
丸くつぶれた形状となる。On the other hand, in the current resin-encapsulated semiconductor device, as shown in FIG. 1, the electrode 2 on the semiconductor die l on the lead frame (not shown) is formed by removing lll5' of the protective insulating film 3. An opening 4a't is provided, and the lead frame 5 and the electrode 2 are connected by a metal wire [6]. At this time, the connecting portion 7 where the thin metal wire 6 contacts the top of the electrode 2 has a rounded shape as shown in FIG.
これに対して、現在の樹脂封止形半導体装置においては
、開孔部4の形状が、第3図に示す様に4角形のため半
導体ダイ1上の配線金属が、電極20開孔部4aにおい
ては保護絶縁膜3に覆われずむき出しになっている。On the other hand, in current resin-sealed semiconductor devices, the shape of the opening 4 is quadrangular as shown in FIG. It is not covered with the protective insulating film 3 and is exposed.
従って、樹脂封止形半導体全高温高湿下で保管ないし、
動作させると外部高湿環境から侵入した水分により、む
き出しの電極部は保護絶縁膜に覆われた内部の配線より
先に腐食奮起こし易く、実用上支障が起こる場合がある
。Therefore, resin-encapsulated semiconductors should not be stored under high temperature and high humidity.
When the device is operated, exposed electrode portions tend to corrode faster than internal wiring covered with a protective insulating film due to moisture entering from an external high-humidity environment, which may cause problems in practical use.
したがって本発明の目的は上記従来技術の欠点金除去し
た有効な樹脂封止形半導体装置を提供することであり、
その特徴は半導体ダイを覆う保護絶縁膜の、電極上開孔
部の形状全、電極部への金属細線の接続部の形状に近い
多角形にすることにある。Therefore, an object of the present invention is to provide an effective resin-sealed semiconductor device that eliminates the disadvantages of the above-mentioned prior art.
The feature is that the entire shape of the opening above the electrode in the protective insulating film covering the semiconductor die is polygonal, which is close to the shape of the connection part of the thin metal wire to the electrode part.
次に本発明を実施例により説明する。Next, the present invention will be explained by examples.
第4図は本発明の一実施例を斜めから見た図であるう図
において、半導体ダイl上の電極の開孔部4bは、金属
細線6の接続部7の丸い形に合わせて六角形にしている
。FIG. 4 is an oblique view of one embodiment of the present invention. In this figure, the opening 4b of the electrode on the semiconductor die l has a hexagonal shape to match the round shape of the connection part 7 of the thin metal wire 6. I have to.
開孔部の形状奮発かり易く示すために上から見た図全第
5図に示す。開孔部4bの形状を六角形にしたために、
むき出しの電極部分は第5図ではほとんど見えない様に
なっているつ
開孔部の形状は六角形以上の円形に近い多角形でも良い
が、現状のマスク技術では斜めのパターンは45度が容
易に精度の高いマスク製作が出来る形であるので、本実
施例では主要な一例として。In order to easily show the shape of the opening, a top view is shown in FIG. 5. Since the shape of the opening 4b is hexagonal,
The exposed electrode part is almost invisible in Figure 5.The shape of the opening may be a hexagon or a polygon close to a circle, but with the current mask technology, a diagonal pattern of 45 degrees is easy. Since this type of mask can be manufactured with high precision, this example will be used as a main example in this embodiment.
六角形の開孔について示しである。A hexagonal opening is shown.
この様に開孔部を円形に近い多角形にすることにより、
電極の、保護絶縁膜が覆っていないむき出しの金属の面
積を大巾に減らし、電極部の腐食を防ぐことが出来る。By making the opening part a polygon close to a circle in this way,
The area of exposed metal on the electrode that is not covered by the protective insulating film can be greatly reduced, and corrosion of the electrode portion can be prevented.
なおかつ、本実施例の様に開孔部の形状全第4図、第5
図で示す様な六角形にすれば、現在のマスク技術で容易
に精度の高いパターンを実現でさる。Furthermore, as in this example, the shape of the opening portion is completely different from that shown in FIGS. 4 and 5.
If the hexagonal shape shown in the figure is used, a highly accurate pattern can be easily realized using current mask technology.
また、この方法は樹脂封止形半導体装置の製造プロセス
において、なんら特別な追加工程を必要とせずきわめて
容易に実現できることを特徴としている。Further, this method is characterized in that it can be realized very easily without requiring any special additional steps in the manufacturing process of resin-sealed semiconductor devices.
第1図は樹脂封止形半導体装置の断面図、第2図は従来
の電極上開孔部の形状を示し文斜視図、第3図は第2図
全土部から見た図、第4図は本発明における一実施例の
電極上開孔部の形状上水した斜視図、第5図は第4図を
上部から見た図である。
尚、図において、1・・・・・・半導体ダイ、2・・・
・・・電極、3・・・・・・保護絶縁膜、4・・・・・
・開孔部3.5・・・・・・リードフレーム、6・・・
・・・金属細線、7・・・・・・接続部である。
、 ゛へ
代理人 弁理士 内 原 1 パh
゛−−2,・′”
% 4 図
奉S 目
−9へ1−Fig. 1 is a cross-sectional view of a resin-sealed semiconductor device, Fig. 2 is a perspective view showing the shape of a conventional opening on an electrode, Fig. 3 is a view seen from the entire area of Fig. 2, and Fig. 4 5 is a perspective view of the shape of the opening on the electrode according to an embodiment of the present invention, and FIG. 5 is a view of FIG. 4 viewed from above. In the figure, 1... semiconductor die, 2...
...Electrode, 3...Protective insulating film, 4...
・Opening part 3.5...Lead frame, 6...
. . . Fine metal wire, 7 . . . Connection portion. , ゛Representative Patent Attorney Uchihara 1 Pah ゛--2,・'” % 4 Zuho S Go to item-9 1-
Claims (1)
半導体ダイの電極と、前記外部へ接続するリードフレー
ム部分とが金属細線で接続されlit脂封市形半導体装
置において、少なくとも半導体ダイ全項う保護絶縁膜の
、電極上開孔部形状が、五角形以上の多角形であること
を特徴とする樹脂封止形半導体装置。[Claims] A lead frame portion on which a semiconductor die is mounted. A lead frame portion connected to the outside is provided, and the electrode of the semiconductor die and the lead frame portion connected to the outside are connected with a thin metal wire, and in a lit sealed semiconductor device, at least all of the semiconductor die is protected. 1. A resin-sealed semiconductor device characterized in that the shape of an opening above an electrode in an insulating film is a polygon of pentagon or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58115525A JPS607757A (en) | 1983-06-27 | 1983-06-27 | Resin seal type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58115525A JPS607757A (en) | 1983-06-27 | 1983-06-27 | Resin seal type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS607757A true JPS607757A (en) | 1985-01-16 |
Family
ID=14664681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58115525A Pending JPS607757A (en) | 1983-06-27 | 1983-06-27 | Resin seal type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS607757A (en) |
-
1983
- 1983-06-27 JP JP58115525A patent/JPS607757A/en active Pending
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