JPS6076121A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6076121A
JPS6076121A JP58185295A JP18529583A JPS6076121A JP S6076121 A JPS6076121 A JP S6076121A JP 58185295 A JP58185295 A JP 58185295A JP 18529583 A JP18529583 A JP 18529583A JP S6076121 A JPS6076121 A JP S6076121A
Authority
JP
Japan
Prior art keywords
mark
electron beam
resist layer
resist
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58185295A
Other languages
Japanese (ja)
Other versions
JPH0644550B2 (en
Inventor
Katsunobu Nakagawa
中川　勝信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58185295A priority Critical patent/JPH0644550B2/en
Publication of JPS6076121A publication Critical patent/JPS6076121A/en
Publication of JPH0644550B2 publication Critical patent/JPH0644550B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To enlarge the step located between a mark established part and the other mark established part, to increase the intensity of a position detecting signal and to obtain high positioning accuracy by a method wherein a protective resist layer is formed on the upper part only of the mark established part, and an etching is performed thereon. CONSTITUTION:The position of a semiconductor wafer 1 is detected by scanning electron beams all over the mark 2 located on the wafer 1, the P type electron beam resist layer part located on a mark established part 3 is selectively coated, and it is inverted to an N type layer. The resist layer part only of a marked part 4 is selectively removed by irradiating electron beams and by performing a developing process. A pattern is drawn on the wafer 1, and resist developing, etching and the like are performed thereon using the resist pattern as a mask. The wafer part corresponding to the marked part 4 can also be etched when the above-mentioned etching process is finished, and a recess 41 is formed. As a result, the step located between the mark established part 3 and the marked part 3 can be increased, the intensity of position detecting signal by the irradiation of electron beams can be increased, and the accuracy of position detection can also be improved.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子ビーム照射による露光で所定の露光用の
位置合せマークを効果的に保護し、高い位置合せ精度の
確保を可能にする製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a manufacturing method that effectively protects alignment marks for predetermined exposure by exposure using electron beam irradiation and makes it possible to ensure high alignment accuracy. .

従来例の構成とその問題点 半導体装置、特に、半導体集積回路の分野では、集積度
の向上を目的とした素子の微細化に対する取り組みが活
発であり、この取り組みの中では、パターンの微細化を
実現することがとりわけ重要である。電子ビーム照射に
よる露光法は、上記のパターンの微細化を実現するだめ
の極めて有用な方法であり、広く採用されるに至ってい
る。Conventional configurations and their problems In the field of semiconductor devices, especially semiconductor integrated circuits, efforts are being made to miniaturize elements to improve the degree of integration. It is especially important to realize this. The exposure method using electron beam irradiation is an extremely useful method for realizing the above-mentioned pattern miniaturization, and has come to be widely adopted.

この電子ビーム照射による露光法では、半導体ウェーハ
表面に形成した露光位置検出用マーク（以下単にマーク
と記す）を露光の直前に電子ビームで走査し、半導体ウ
ェーハの位置を正しく検出することが一般に行なわれて
いる。そして、この位置検出が終了した後は、マーク部
を電子ビームで全面走査しく以下塗りつぶしと記す）、
この後の処理工程でマークが損傷することのないようレ
ジスト膜を残してマークを保護している。In this exposure method using electron beam irradiation, an exposure position detection mark (hereinafter simply referred to as mark) formed on the surface of the semiconductor wafer is generally scanned with an electron beam just before exposure to accurately detect the position of the semiconductor wafer. It is. After this position detection is completed, the entire mark is scanned with an electron beam (hereinafter referred to as "filled"),
A resist film is left to protect the marks so that they will not be damaged in subsequent processing steps.

ところで、レジストとしてネガ形の電子線レジストが使
用されている場合には、マークの塗りつぶしに要する時
間は比較的短いが、ポジ形の電子線レジストが使用され
ている場合には、電子線レジストがオーバ露光され、ポ
ジ形からネガ形への反転が生じるまでの間にわたり塗り
つぶしを施さねばならない。電子線レジストにポジ形か
らネガ形への反転を発生させるために必要とされる露光
量は、パターンを描画するときの露光量の１００倍以上
である。したがって、マークの塗りつぶしに要する時間
が極めて長くなる。By the way, when a negative-tone electron beam resist is used as the resist, the time required to fill in the mark is relatively short, but when a positive-tone electron beam resist is used, the electron beam resist Filling must be performed until overexposure occurs and the reversal from positive to negative occurs. The amount of exposure required to cause the electron beam resist to undergo reversal from positive to negative is 100 times or more the amount of exposure used when drawing a pattern. Therefore, the time required to fill in the mark becomes extremely long.

第１図および第２図は１、上記の方法によりマークの塗
りつぶしを行ない、マーク保護のためのレジスト膜を形
成する過程を説明するだめの図であり、第１図ａは半導
体ウェーハ上に形成されたマークの平面図、第１図すは
第１図ａのＢ−Ｂ線に沿った断面図、第２図ａはマーク
保護がなされたのちの平面図そして第２図すは第２図ａ
のＢ−Ｂ線に沿った断面図を示す。第１図で示すように
、半導体ウェーハ１の所定域に形成されたマーク２は、
たとえば、半導体ウェーハの主面から突出するマーク確
定部分３とこれ以外のマーク部４とで構成されている。1 and 2 are diagrams for explaining the process of filling in marks by the method described above and forming a resist film to protect the marks. Figure 1 is a cross-sectional view taken along the line B-B in Figure 1a, Figure 2a is a plan view after the mark has been protected, and Figure 2 is a cross-sectional view taken along line B-B in Figure 1a. a
A cross-sectional view taken along line B-B of FIG. As shown in FIG. 1, the mark 2 formed in a predetermined area of the semiconductor wafer 1 is
For example, it is composed of a mark defining portion 3 protruding from the main surface of the semiconductor wafer and a mark portion 4 other than this.

電子ビーム走査による位置検出は、マーク確定部分３と
他のマーク部分４とからなるマークの全域を走査するこ
とによりなされる。Position detection by electron beam scanning is performed by scanning the entire area of the mark consisting of the mark-determined portion 3 and other mark portions 4.

なお、半導体ウェー・・１の表面全域にはレジスト層６
が形成されており、このレジスト層を保護膜としてマー
ク上に残すため、位置検出が終了し、パターンの描画に
入る以前に塗りつぶすわけであるが、このレジスト層６
がポジ形の電子線レジストであるときには、これがネガ
形に反転するまでくり返して塗りつぶしを実施する。こ
ののち、レジストの現像を行なうことにより、第２図で
示すようにマーク上に保護用レジスト層６が形成され、
以後に実施されるエツチング工程におけるマークのエツ
チングあるいは損傷が防止される。このような従来の方
法によっても、マーク保護の目的は達成されるものの、
塗りつぶしに多大の時間が費いやされることは避けられ
ない。この不都合を除くための方法として半導体ウェー
ハ上に多数のマークを設け、１度の位置検出のために１
つのマークを使用し、使用済みのマークに対する保護を
排するようにした方法もあるが、この方法では、マーク
による半導体ウェーハ上の占拠面積が大きくなり、半導
体ウェーへの利用率が低下する不都合が派生する。Note that a resist layer 6 is formed over the entire surface of the semiconductor wafer 1.
is formed, and in order to leave this resist layer on the mark as a protective film, it is painted over after position detection is completed and before pattern drawing begins.
When is a positive electron beam resist, filling is repeated until it is inverted to a negative resist. Thereafter, by developing the resist, a protective resist layer 6 is formed on the mark as shown in FIG.
Etching or damage to the marks in subsequent etching steps is prevented. Although the purpose of mark protection can be achieved by such conventional methods,
It is inevitable that a large amount of time will be spent filling in the data. As a method to eliminate this inconvenience, a large number of marks are provided on the semiconductor wafer, and one mark is used for one-time position detection.
There is also a method that uses two marks and eliminates protection for used marks, but this method has the disadvantage that the mark occupies a large area on the semiconductor wafer, reducing the utilization rate of the semiconductor wafer. Derive.

発明の目的 本発明は、レジストとしてポジ形の電子線レジストが使
用される条件の下で、マーク保護のだめの塗りつぶしに
要する時間を大幅に短縮す鼠ことかでき、しかも、高い
位置検出精度を得ることもできる半導体装置の製造方法
の提供を目的とするものである。Purpose of the Invention The present invention makes it possible to significantly reduce the time required to fill in the mark protection pot under the condition that a positive electron beam resist is used as the resist, and to obtain high position detection accuracy. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can also be used.

発明の構成 本発明の半導体装置の製造方法は、半導体基板上に形成
したマーク確定部分を含む位置合せ用のマーク上を覆う
ポジ形電子線レジスト層の前記マーク確定部分上もしく
は他のマーク部分上のポジは他のマーク部分のいずれか
一方の上部にのみ層膜用レジスト層を形成するようにし
た方法である。Structure of the Invention The method for manufacturing a semiconductor device of the present invention provides a method for manufacturing a semiconductor device, in which a positive electron beam resist layer covering an alignment mark including a mark defined portion formed on a semiconductor substrate is formed on the mark defined portion or other mark portions. The positive method is a method in which a resist layer for layer film is formed only on top of one of the other mark portions.

この製造方法によれば、位置検出ののちのマークの塗シ
つぶし面積が小さくなるばかりでなく、マーク確定部分
またはマーク部分のいずれかの側の保護を意図的に排除
したことにより、この部分が、この後のエツチング処理
でエツチングされ、マーク確定部分が強調されることに
なる。According to this manufacturing method, not only does the filled area of the mark after position detection become smaller, but also this area is , will be etched in the subsequent etching process, and the marked part will be emphasized.

実施例の説明 以下、第３図〜第７図を参照して本発明の詳細な説明す
る。DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to FIGS. 3 to 7.

本発明の半導体装置の製造方法でも、第３図で示すよう
に、半導体ウェーハ１の所定域に位置検出用のマーク２
が形成され、さらに、このマーク上がポジ形電子線レジ
スト層５で覆われたものが使用されており、この限りで
は、第１図で示した従来法のものと同じである。この半
導体ウェーハ１上のマークの全域を電子ビームで走査し
、半導体ウェーハの位置検出を行ない、次いで、マーク
確定部分３の上に位置するポジ形電子線レジスト層部分
を選択的に塗りつぶし、この部分をネガ形に反転させる
。こののち、マーク２の全域を電子ビームで照射し、引
き続いて現像を行うと、電子ビームで適正露光されたマ
ーク部分４の上を覆うポジ形電子線レジスト層部分のみ
が選択的に除かれる。Also in the method of manufacturing a semiconductor device of the present invention, as shown in FIG.
is formed, and the mark is further covered with a positive electron beam resist layer 5. In this respect, it is the same as the conventional method shown in FIG. The entire area of the mark on the semiconductor wafer 1 is scanned with an electron beam to detect the position of the semiconductor wafer, and then the positive electron beam resist layer portion located on the mark defined portion 3 is selectively filled in. Flip to negative form. Thereafter, when the entire area of the mark 2 is irradiated with an electron beam and development is performed subsequently, only the portion of the positive electron beam resist layer covering the mark portion 4 properly exposed to the electron beam is selectively removed.

第４図は、この処理が施されたのちの状態を゛示す図で
あり、突出したマーク確定部分３の上面には保護用レジ
スト層６が存在し、マーク部分４の上のレジスト層が全
て除かれた状態が得られる。FIG. 4 is a diagram showing the state after this process, in which a protective resist layer 6 is present on the upper surface of the protruding mark-defining portion 3, and the entire resist layer above the mark portion 4 is completely removed. The removed state is obtained.

このようにして、マーク保護を行なったのち、パターン
の描画、レジストの現像およびレジスレ（ターンをマス
クとしたエツチング処理等が半導体ウェーハに対して施
される。After mark protection is performed in this manner, the semiconductor wafer is subjected to pattern drawing, resist development, resist scratching (etching using a turn as a mask, etc.), and the like.

第６図は、半導体ウェーッ・に対してエツチング処理が
施されたのちの状態を示す図であり、エツチング時にマ
ーク部分４に対応する半導体ウェー八部分が露出してい
るために、この部分もエツチングされる。したがって、
図示するように、凹所４１が形成されるところとなり、
マーク確定部分３の上面とマーク部分４の面との間の段
差はエツチング処理の前よりも大きくなる。このような
段差の増大は、電子ビーム照射による位置検出の信号強
度を高め、位置検出精度の向上をもたらす。FIG. 6 is a diagram showing the state after the semiconductor wafer has been subjected to the etching process.Since the portion of the semiconductor wafer corresponding to the mark portion 4 is exposed during etching, this portion is also etched. be done. therefore,
As shown, a recess 41 is formed,
The difference in level between the upper surface of the mark defined portion 3 and the surface of the mark portion 4 becomes larger than before the etching process. Such an increase in the level difference increases the signal strength for position detection by electron beam irradiation, resulting in an improvement in position detection accuracy.

第６図および第７図に、本発明に関連して行なった確認
実験の結果を示す。第６図は、マークの段差Ｈを横軸に
、位置検出信号強度Ｓの相対値を縦軸にとり、両者の関
係を示した図、また、第７図は、ポジ形電子線レジスト
のネガ形反転面積Ａを横軸に、電子ビームの照射時間Ｔ
の相対値を縦軸にとり、両者の関係を示した図である。6 and 7 show the results of confirmation experiments conducted in connection with the present invention. Fig. 6 shows the relationship between the mark step H on the horizontal axis and the relative value of the position detection signal strength S on the vertical axis, and Fig. 7 shows the negative form of the positive electron beam resist. With the inversion area A as the horizontal axis, the electron beam irradiation time T
FIG. 3 is a diagram showing the relationship between the two, with the vertical axis representing the relative value of .

第６図から明らかなように、マークの段差Ｈの増加によ
り位置検出信号強度Ｓが増し、また、第７図から明らか
なように、ネガ形反転面積Ａと電子ビーム照射時間Ｔの
間には比例関係の成立することが確認された。As is clear from FIG. 6, the position detection signal strength S increases as the mark step H increases, and as is clear from FIG. It was confirmed that a proportional relationship holds.

以上、本発明を一例を示して説明したが、マーク確定部
分を半導体ウェーハの主面に対して窪ませる構造とする
こともできる。この場合には、マーク上のポジ形電子線
レジスト層の塗シっぷしをマーク確定部分を除く他のマ
ーク部分上に限定し、保護用レジスト層の形成部を実施
例とは逆にする。Although the present invention has been described above with reference to an example, it is also possible to adopt a structure in which the mark determination portion is recessed relative to the main surface of the semiconductor wafer. In this case, the application of the positive electron beam resist layer on the mark is limited to the other mark parts except for the mark definite part, and the formation part of the protective resist layer is reversed from that in the embodiment.

このような関係で保護用レジスト層をマーク上に形成す
ると、エツチングによりマーク確定部分がエツチングさ
れ、したがって、実施例とはマークのエツチング位置が
逆になるが、段差Ｈはエツチング処理の前よりも大きく
なる。さらに、マーク確定部分を凹形あるいは凸形とす
ることにかえて、半導体基板とは異る物質、たとえば、
金（Ａｕ）　などで形成し、マークを平坦なものとする
こともできる。When a protective resist layer is formed on the mark in this manner, the mark definite part is etched, and therefore the etching position of the mark is reversed from the example, but the step H is higher than before the etching process. growing. Furthermore, instead of making the mark determination part concave or convex, it is possible to use a material different from the semiconductor substrate, for example,
It is also possible to make the mark flat by forming it from gold (Au) or the like.

発明の効果 本発明の製造方法では、マーク上を覆うポジ形電子線レ
ジスト層の全域を塗りつぶす必要がなく、マーク確定部
分または他のマーク部分上の領域のみを塗りつぶせばよ
いため、露光時間を大幅に短縮することができること、
パターン描画ののちのエツチングでマーク確定部分と他
のマーク部分との間の段差が大きくなるため、位置検出
信号の強度が増し、高い位置合せ精度が得られること、
さらに、多数のマークを形成する必要がなく、半導体ウ
ェーハの利用率の低下を防止できることなどの効果が奏
される。Effects of the Invention In the manufacturing method of the present invention, there is no need to fill in the entire area of the positive electron beam resist layer that covers the mark, and it is only necessary to fill in the area on the mark definite part or other mark parts, so the exposure time can be significantly reduced. that it can be shortened to
Etching after pattern drawing increases the level difference between the marked part and other marked parts, increasing the strength of the position detection signal and achieving high alignment accuracy.
Furthermore, it is not necessary to form a large number of marks, and a reduction in the utilization rate of the semiconductor wafer can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来の方法によりマークの塗りつ
ぶしを行ない、マーク保護のためのレジスト膜を形成す
る過程を説明するだめの図で、第造方法によりマーク保
護のためのレジスト膜が形感される状態を説明するため
の図で、第３図ａ〜強度とマークの段差の関係およびネ
ガ形反転面積と電子ビーム照射時間の関係を示す図であ
る。 １・・・・・・半導体ウェーハ、２・・・・・・位置合
せ用のマーク、３・・・・・・マーク確定部分、４・・
・・・・マーク確定部分以外のマーク部分、６・・・・
・・ポジ形電子線レジスト層、６・・・・・・ネガ形化
したレジスト層、４１・・・・・・凹所。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 ６図 →ＨＣｐｍン 一：Ａ７図 →　Ａ　（ｍｍＦ）Figures 1 and 2 are diagrams for explaining the process of filling in marks and forming a resist film to protect marks using the conventional method. This is a diagram for explaining the perceived state, and is a diagram showing the relationship between the intensity and the level difference of the mark, and the relationship between the negative inversion area and the electron beam irradiation time. 1... Semiconductor wafer, 2... Alignment mark, 3... Mark confirmed portion, 4...
...marked part other than the mark confirmed part, 6...
. . . Positive electron beam resist layer, 6 . . . Negative resist layer, 41 . . . Recess. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 6 → HCpm-1: Figure A7 → A (mmF)

Claims (1)

【特許請求の範囲】 （１）半導体基板上に形成したマーク確定部分を含む位
置合せ用のマーク上を覆うポジ形電子線レジしてネガ形
に反転させたのち、ネガ形に反転するジ形電子線レジス
ト層にパターンを描画すること−を特徴とする半導体装
置の製造方法。 ？）マーク確定部分が半導体基板主面から突出腰この上
部のポジ形電子線レジスト層部分がネガ形に反転させら
れることを特徴とする特許請求の範囲第１項に記載の半
導体装置の製造方法。 （３）マーク確定部分が半導体基板に設けた凹所で形成
され、同マーク確定部分を除く他のマーク部上のポジ形
電子線レジスト層部分がネガ形に反転させられることを
特徴とする特許請求の範囲第１[Scope of Claims] (1) Positive electron beam registration that covers the positioning mark including the mark-determined portion formed on the semiconductor substrate, and then reversed to the negative shape. A method for manufacturing a semiconductor device, comprising drawing a pattern on an electron beam resist layer. ? 2.) The method for manufacturing a semiconductor device according to claim 1, wherein the mark-defining portion protrudes from the main surface of the semiconductor substrate, and the positive electron beam resist layer portion above the portion is inverted into a negative shape. (3) A patent characterized in that the mark defined portion is formed by a recess provided in a semiconductor substrate, and the positive electron beam resist layer portions on other mark portions other than the mark defined portion are reversed into negative shapes. Claim 1
JP58185295A 1983-10-03 1983-10-03 Method for manufacturing semiconductor device Expired - Lifetime JPH0644550B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58185295A JPH0644550B2 (en) 1983-10-03 1983-10-03 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58185295A JPH0644550B2 (en) 1983-10-03 1983-10-03 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6076121A true JPS6076121A (en) 1985-04-30
JPH0644550B2 JPH0644550B2 (en) 1994-06-08

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ID=16168356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58185295A Expired - Lifetime JPH0644550B2 (en) 1983-10-03 1983-10-03 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0644550B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982603A (en) * 1995-09-12 1997-03-28 Toshiba Corp Misalignment evaluation in electron beam lithography equipment

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223404A (en) * 1999-02-02 2000-08-11 Nikon Corp Method for detecting mark for alignment in charged particle beam exposure system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982603A (en) * 1995-09-12 1997-03-28 Toshiba Corp Misalignment evaluation in electron beam lithography equipment

Also Published As

Publication number Publication date
JPH0644550B2 (en) 1994-06-08

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