JPS6074504A - Thick film condenser - Google Patents
Thick film condenserInfo
- Publication number
- JPS6074504A JPS6074504A JP58180461A JP18046183A JPS6074504A JP S6074504 A JPS6074504 A JP S6074504A JP 58180461 A JP58180461 A JP 58180461A JP 18046183 A JP18046183 A JP 18046183A JP S6074504 A JPS6074504 A JP S6074504A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- substrate
- dielectric layer
- thickness
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
発明の技術分野
本発明は厚膜混成集積回路に係り、特に厚膜混成集積回
路における厚膜コンデンサに関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to thick film hybrid integrated circuits, and more particularly to thick film capacitors in thick film hybrid integrated circuits.
技術の背景
電子機器の多機能・複雑化、小形・軽量化が進むにつれ
て、ハイブリッドＩＣすなわち混成集積回路がよシその
必要性を増大させている。混成集積回路は幾つかの異々
った材料を使用して構成されている点がほとんど単一の
材料（８１）ｅ用いているモノリシロクＩＣと基本的に
違っている。このような混成集積回路では１導以上の厚
さの膜を導体と抵抗体に用いる場合厚膜混成集積回路と
称されている。Background of the Technology As electronic devices become more multifunctional, more complex, smaller, and lighter, the need for hybrid ICs, that is, hybrid integrated circuits, increases. Hybrid integrated circuits are fundamentally different from monolithic ICs, which mostly use a single material (81), in that they are constructed using several different materials. In such a hybrid integrated circuit, when a film having a thickness of one conductor or more is used as a conductor and a resistor, it is called a thick film hybrid integrated circuit.
従来技術と問題点
従来、厚膜混成集積回路におけるコンデンサは導体と誘
電率の高い絶縁膜とを交互に重ねる厚膜印刷によって例
えばセラミック、アルミナ等の基板上に形成される場合
と例えばチップ形積層セラミックコンデンサ等のような
チップコンデンサを上記基板上に形成される場合とが知
られている。Conventional technology and problems Conventionally, capacitors in thick film hybrid integrated circuits have been formed on substrates such as ceramic or alumina by thick film printing in which conductors and insulating films with a high dielectric constant are alternately laminated, and in other cases, capacitors have been formed on substrates such as ceramic or alumina, and in other cases, capacitors have been formed on substrates such as ceramic or alumina, for example. It is known that a chip capacitor such as a ceramic capacitor is formed on the substrate.
上記厚膜印刷法等によって基板上に形成されるコンデン
サは基板上で例えば比誘率ε、＝２５０（誘電率６＝６
．・ｇｏ＝８．８５４Ｘ１０−” Ｘ１００＝８．８５
４ Ｘ１０ ［Ｃ−Ｎ’″・ｍ 〕誘電体膜厚４０μ、
で１０００ＰＦのコンデンサを形成する場合１８胴２程
度の大きな表面積が必要である。しかしながらこのよう
な大きな表面積を要する構造のコンデンサは小形化・高
集積化の方向に逆行するものである。A capacitor formed on a substrate by the above-mentioned thick film printing method has a relative permittivity ε=250 (permittivity 6=6
．．・go=8.854X10-"X100=8.85
4 X10 [C-N'''・m] Dielectric film thickness 40μ,
When forming a 1000PF capacitor, a large surface area of about 18 cylinders and 2 is required. However, capacitors having such a structure that require a large surface area go against the trend of miniaturization and high integration.
発明の目的
上記欠点を鑑み本発明は小型化・集積化を図った厚膜混
成集積回路を提供することを目的とする。OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, it is an object of the present invention to provide a thick film hybrid integrated circuit that is smaller and more integrated.
発明の構成
本発明の目的は基板に形成したスルーホールに順次第１
導体層、誘電体層、第２導体層、そしてオーバーコート
を配設してなることを特徴とする厚膜コンデンサによっ
て達成される。Structure of the Invention The object of the present invention is to sequentially fill through holes formed in a substrate with
This is achieved by a thick film capacitor characterized by a conductor layer, a dielectric layer, a second conductor layer, and an overcoat.
発明の実施例 以下本発明の１実施例を図面に基づいて説明する。Examples of the invention An embodiment of the present invention will be described below based on the drawings.
図は本発明の１実施例を示す概略断面図である。The figure is a schematic sectional view showing one embodiment of the present invention.
図において１はセラミック基板、２はＡｇ−Ｐｄ導体か
らなり、厚さ１０μを有する浅溝体層、３は例えばチタ
ン酸バリウムペースト焼成物からなり、厚さ２０μを有
する表誘電体層、４は例えばチタン酸バリウムペースト
焼成物からなり厚さ２０μを有する裏誘電体層、５は例
えばＡｇ−Ｐｄ導体からなり、厚さ１０μを有する裏溝
体層６は厚さ２０μを有する表オーバーコートガラス、
７は厚さ２０μを有する裏オーバーコートガラスでちゃ
、Ａはスルーホールである。In the figure, 1 is a ceramic substrate, 2 is a shallow groove layer made of an Ag-Pd conductor and has a thickness of 10μ, 3 is a surface dielectric layer made of, for example, a barium titanate paste fired product and has a thickness of 20μ, and 4 is a surface dielectric layer having a thickness of 20μ. For example, the back dielectric layer 5 is made of a fired product of barium titanate paste and has a thickness of 20μ;
7 is a back overcoat glass having a thickness of 20μ, and A is a through hole.
このようにスルーホールＡに形成される厚膜コンデンサ
は従来、基板上に形成したのとは異なり、スルーホール
穴径を１蝙φ基板厚さを０．６３５隠とすれば約６０係
面積が縮少される。The thick film capacitor formed in the through-hole A in this way is different from conventionally formed on the substrate, and has a coefficient area of approximately 60, assuming that the through-hole diameter is 1 mm and the substrate thickness is 0.635 mm. reduced.
なお上記実施例は厚膜印刷技術によって作られる。すな
わち先ず基板上に浅溝体層２を印刷しスルホールＡの裏
側から真空吸引し、一部スルーホールＡ内に引き込む。Note that the above embodiments are made by thick film printing technology. That is, first, the shallow groove layer 2 is printed on the substrate, and a vacuum is applied from the back side of the through hole A to partially draw it into the through hole A.
次に該浅溝体層を１０分間乾燥した後、約８５０℃で焼
成する。同様に表誘電体層３全印刷し、真空吸引により
一部スルーホールＡ内に弓私み、乾燥、焼成を行う、次
に基板１の裏側から裏誘電体層、裏導体層をそれぞれ印
刷し、スルーホールＡ内へ真空吸引し、次に乾燥焼成を
行なう。最後にオーバーコートガラスを印刷、乾燥焼成
して完成される。Next, the shallow groove layer is dried for 10 minutes and then fired at about 850°C. In the same way, the entire front dielectric layer 3 is printed, a portion of the through hole A is filled with vacuum suction, dried, and baked. Next, the back dielectric layer and the back conductor layer are printed from the back side of the substrate 1, respectively. , a vacuum is drawn into the through hole A, and then drying and firing are performed. Finally, the overcoat glass is printed, dried and fired.
本発明に用いられる導体及び誘電体は通常使用される材
料が有効に用いられる。As the conductor and dielectric material used in the present invention, commonly used materials can be effectively used.
発明の詳細
な説明したように本発明によれば厚膜コンデンサを小型
化、集積化可能になるのでそれに伴なって小型化、集積
化された厚膜混成集積回路を得ることが出来る。As described in detail, according to the present invention, thick film capacitors can be downsized and integrated, and accordingly, a thick film hybrid integrated circuit that is downsized and integrated can be obtained.
図は本発明の１実施例を示す概略断面図である。
１・・・セラミ、り基板、２・・・浅溝体層、３・・・
表誘電体層、４・・・裏誘電体層、５・・・裏溝体層、
６・・・表オーバーコートガラス、７・・・裏オーバー
コートフラス。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士 西 舘 和 之
弁理士 内 １）幸 男
弁理士 山 口 昭 之
く〜ノーー１、The figure is a schematic sectional view showing one embodiment of the present invention. 1... Ceramic substrate, 2... Shallow groove layer, 3...
Front dielectric layer, 4... Back dielectric layer, 5... Back groove layer,
6... Front overcoat glass, 7... Back overcoat glass. Patent Applicant: Fujitsu Limited Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate 1) Yukio Patent Attorney Akira Yamaguchi - No. 1
Claims (1)
電体層、第２導体層、そしてオーバーコートを配設して
なることを特徴とする厚膜コンデンサ。1. A thick film capacitor characterized in that a first conductor layer, a dielectric layer, a second conductor layer, and an overcoat are sequentially disposed in a through hole formed in a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58180461A JPS6074504A (en) | 1983-09-30 | 1983-09-30 | Thick film condenser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58180461A JPS6074504A (en) | 1983-09-30 | 1983-09-30 | Thick film condenser |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6074504A true JPS6074504A (en) | 1985-04-26 |
Family
ID=16083625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58180461A Pending JPS6074504A (en) | 1983-09-30 | 1983-09-30 | Thick film condenser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074504A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6380862U (en) * | 1986-11-17 | 1988-05-27 |
-
1983
- 1983-09-30 JP JP58180461A patent/JPS6074504A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6380862U (en) * | 1986-11-17 | 1988-05-27 |
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