JPH0666218B2 - Multilayer thin film capacitor and manufacturing method thereof - Google Patents

Multilayer thin film capacitor and manufacturing method thereof

Info

Publication number
JPH0666218B2
JPH0666218B2 JP14477690A JP14477690A JPH0666218B2 JP H0666218 B2 JPH0666218 B2 JP H0666218B2 JP 14477690 A JP14477690 A JP 14477690A JP 14477690 A JP14477690 A JP 14477690A JP H0666218 B2 JPH0666218 B2 JP H0666218B2
Authority
JP
Japan
Prior art keywords
ceramic substrate
layer
thin film
internal electrode
film capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14477690A
Other languages
Japanese (ja)
Other versions
JPH0437105A (en
Inventor
幹夫 羽賀
利文 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14477690A priority Critical patent/JPH0666218B2/en
Publication of JPH0437105A publication Critical patent/JPH0437105A/en
Publication of JPH0666218B2 publication Critical patent/JPH0666218B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明は、小形,軽量,低コスト化を図った積層薄膜コ
ンデンサおよびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer thin film capacitor that is small, lightweight and low cost, and a method for manufacturing the same.

従来の技術 近年、機器の小形・軽量化志向、高集積回路の採用によ
る電子回路の高密度化あるいは自動挿入機の普及などに
ともない、電子部品に対する小形化の要請がますます強
くなってきている。その中にあって、コンデンサも同様
に小形化へと種々の開発が試みられている。周知のよう
に、コンデンサの単位体積当たりの静電容量は、誘電体
の誘電率に比例し、誘電体の厚さに反比例する。したが
って、コンデンサの小形化を図るためには、誘電体の誘
電率を大きくするか、または誘電体の厚さを薄くするこ
とにより大幅な小形化が実現できることから薄膜コンデ
ンサについては既に多くの検討が行われており、薄膜コ
ンデンサの薄膜積層方法および積層構造は公知である
(例えば、特開昭55−91112号公報,特開昭56
−144523号公報参照)。すなわち、真空蒸着法,
スパッタリング法等の物理的気相成長法(PVD法)に
より形成されるパラジウム,銀,銅,ニッケル,アルミ
ニウム等からなる内部電極層と酸化アルミニウム,酸化
珪素,酸化チタン,チタン酸ストロンチウム等からなる
誘電体層とを交互に積層した薄膜コンデンサが一般に知
られている。
2. Description of the Related Art In recent years, there has been an increasing demand for miniaturization of electronic components with the trend toward smaller and lighter equipment, higher density of electronic circuits due to the adoption of highly integrated circuits, and the spread of automatic insertion machines. . Among them, various developments have been attempted to miniaturize the capacitors as well. As is well known, the capacitance per unit volume of a capacitor is proportional to the permittivity of the dielectric and inversely proportional to the thickness of the dielectric. Therefore, in order to reduce the size of the capacitor, it is possible to achieve a large size reduction by increasing the dielectric constant of the dielectric or by reducing the thickness of the dielectric.Thus, many studies have already been conducted on thin film capacitors. The method of laminating thin films and the laminated structure of thin film capacitors are known (for example, JP-A-55-91112 and JP-A-56).
(See Japanese Patent Publication No. 144523). That is, the vacuum deposition method,
Internal electrode layers made of palladium, silver, copper, nickel, aluminum, etc. formed by a physical vapor deposition method (PVD method) such as sputtering method, and dielectrics made of aluminum oxide, silicon oxide, titanium oxide, strontium titanate, etc. A thin film capacitor in which body layers are alternately laminated is generally known.

このように従来の薄膜コンデンサでは、真空蒸着法,ス
パッタリング法等の物理的気相成長法(PVD法)を用
いて、内部電極層および誘電体層を、表面粗さの小さ
い、平滑な絶縁基板上に形成することにより、大幅な薄
膜化が可能となり、これによりコンデンサの小形化が図
られてきた。すなわち、ガラス基板またはグレーズ処理
を施したセラミック基板のような表面粗さの小さい、平
滑な絶縁基板においては、基板表面の凹凸が小さいた
め、真空蒸着法,スパッタリング法等の物理的気相成長
法(PVD法)を用いて形成される極薄の内部電極層お
よび誘電体層は基板表面の凹凸に十分追従することがで
き、内部電極層および誘電体層ともに均一な膜厚を得る
ことができる。これにより、コンデンサとして必要な耐
電圧特性を損うことなく薄膜積層部を形成することが可
能となる。
As described above, in the conventional thin film capacitor, the internal electrode layer and the dielectric layer are formed on the smooth insulating substrate having a small surface roughness by using the physical vapor deposition method (PVD method) such as the vacuum deposition method and the sputtering method. By forming it on the top surface, it is possible to significantly reduce the film thickness, which has led to miniaturization of the capacitor. That is, in a smooth insulating substrate having a small surface roughness such as a glass substrate or a ceramic substrate subjected to a glaze treatment, the unevenness of the substrate surface is small, and therefore physical vapor deposition methods such as vacuum deposition method and sputtering method are used. The ultra-thin internal electrode layer and the dielectric layer formed by using the (PVD method) can sufficiently follow the irregularities on the substrate surface, and a uniform film thickness can be obtained for both the internal electrode layer and the dielectric layer. . This makes it possible to form the thin film laminated portion without impairing the withstand voltage characteristics required for the capacitor.

発明が解決しようとする課題 このような従来の積層薄膜コンデンサでは、ガラス基板
またはグレーズ層を形成したセラミック基板のような表
面粗さの小さい、平滑な絶縁基板を用いると、外部電極
層の基板への付着強度が極めて低くなり、特性上弊害と
なる。また逆に表面粗さが大きいセラミック基板等の絶
縁基板を用いると、金属溶射法により形成される外部電
極の絶縁基板への付着強度は十分に得られるが、コンデ
ンサとして必要な耐電圧特性が低下するため、内部電極
層および誘電体層の大幅な薄膜化は困難であり、薄膜コ
ンデンサの小形,軽量,低コスト化が実現されないとい
う課題があった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a conventional multilayer thin film capacitor, when a smooth insulating substrate having a small surface roughness, such as a glass substrate or a ceramic substrate on which a glaze layer is formed, is used, it becomes Has extremely low adhesion strength, which is an adverse effect on the characteristics. On the other hand, if an insulating substrate such as a ceramic substrate with a large surface roughness is used, the adhesion strength of the external electrode formed by the metal spraying method to the insulating substrate can be sufficiently obtained, but the withstand voltage characteristics required as a capacitor are deteriorated. Therefore, it is difficult to significantly reduce the thickness of the internal electrode layers and the dielectric layer, and there is a problem in that the thin film capacitor cannot be made compact, lightweight and low cost.

本発明は上記課題を解決するもので、大幅な小形,軽
量,低コスト化を図った高品質の積層薄膜コンデンサお
よびその製造方法を提供することを目的としている。
The present invention solves the above problems, and an object of the present invention is to provide a high quality multilayer thin film capacitor that is significantly small in size, light in weight and low in cost, and a manufacturing method thereof.

課題を解決するための手段
本発明は上記目的を達成するために、少なくとも一主
面上の両端部を除く領域にグレーズ層を形成したセラミ
ック基板と、前記グレーズ層上に誘電体層を間に介在さ
せて積層され各一端が前記グレーズ層を越えて前記セラ
ミック基板の両端部に一層毎交互に延長して配設された
一対の内部電極層と、前記積層された一対の内部電極層
および誘電体層上に前記セラミック基板の両端部を除い
て形成された保護膜と、その保護膜により被覆されてい
ない前記内部電極層の延長部分の前記セラミック基板の
両端部に形成された外部電極層とを有する構成よりな
る。
Means for solving the problem
In order to achieve the above object, the present invention provides a ceramic substrate having a glaze layer formed on at least one main surface except both ends thereof, and a dielectric layer on the glaze layer, which is laminated at each end. A pair of internal electrode layers that are alternately extended to both ends of the ceramic substrate beyond the glaze layer, and the ceramic substrate on the laminated pair of internal electrode layers and dielectric layers. Of the external electrode layer formed on both ends of the ceramic substrate, which is an extended portion of the internal electrode layer not covered by the protective film.

作用 上記の構成により表面粗さの小さいグレーズ層上に内部
電極層および誘電体層を形成することによる耐電圧特性
の向上と、表面粗さの比較的大きいセラミック基板両端
部に内部電極層を延長して形成することによる外部電極
層の付着強度の増大が起る。
Action With the above configuration, the internal electrode layer and the dielectric layer are formed on the glaze layer with a small surface roughness to improve the withstand voltage characteristics, and the internal electrode layers are extended to both ends of the ceramic substrate with a relatively large surface roughness. As a result, the adhesion strength of the external electrode layer increases.

実施例 以下、本発明の一実施例について、第1図を参照しなが
ら説明する。
Embodiment An embodiment of the present invention will be described below with reference to FIG.

図に示すように、セラミック基板1の上にグレーズ層2
がセラミック基板1の両端部を除いて形成され、その上
に一対の内部電極層3と誘電体層4とが交互に積層され
て薄膜コンデンサが形成され、さらにその上に保護膜5
が内部電極層3の非対向部の両端部に近い一部分を除く
薄膜コンデンサ部とその周辺のグレーズ処理されたセラ
ミック基板1の表面を覆うように形成された後、内部電
極層3の保護膜5によって覆われていない部分を含むセ
ラミック基板1の両端部に外部電極層6が形成されてい
る。
As shown in the figure, the glaze layer 2 is formed on the ceramic substrate 1.
Is formed except for both ends of the ceramic substrate 1, and a pair of internal electrode layers 3 and dielectric layers 4 are alternately laminated thereon to form a thin film capacitor, and a protective film 5 is further formed thereon.
Is formed so as to cover the surface of the thin film capacitor portion except for the portions near both ends of the non-opposing portion of the internal electrode layer 3 and the surface of the glaze-treated ceramic substrate 1 around the thin film capacitor portion, and then the protective film 5 for the internal electrode layer 3 is formed. External electrode layers 6 are formed on both ends of the ceramic substrate 1 including a portion not covered by.

セラミック基板1としては、表面実装時の高温に耐え、
かつ安価なものであれば、アルミナ等の無機系のいずれ
の材料でも使用できる。このセラミック基板1の表面粗
さは、平均中心線粗さで0.1μm以上であることが望
ましい。セラミック基板1の表面粗さの改善のため形成
されるグレーズ層2の表面粗さは、平均中心線粗さで
0.01μm以下であることが望ましい。
As the ceramic substrate 1, it can withstand high temperatures during surface mounting,
Any inorganic material such as alumina can be used as long as it is inexpensive. The surface roughness of the ceramic substrate 1 is preferably 0.1 μm or more in average center line roughness. The surface roughness of the glaze layer 2 formed to improve the surface roughness of the ceramic substrate 1 is preferably 0.01 μm or less in average center line roughness.

次に、本発明をより明確にするため、以下実際の実施例
(1)および(2)と特性を比較するための比較例(1),(2)お
よび(3)について説明する。
Next, in order to clarify the present invention more clearly,
Comparative examples (1), (2) and (3) for comparing the characteristics with (1) and (2) will be described.

(実施例(1)) 表面の平均中心線粗さ(Ra)が0.5μmのアルミナ
のセラミック基板1上に、セラミック基板1の両端部を
除いて25μm厚のグレーズ層2(Ra:0.005μ
m)を形成した後、その上に内部電極層3として真空蒸
着法にて膜厚0.05μmのアルミニウム膜を、誘電体
層4として蒸着重合法により膜厚0.4μmの芳香族ポ
リイミド薄膜を、交互に15層積層した後、窒化シリコ
ンからなる保護膜5を形成し、さらに減圧プラズマ溶射
法によって25μm厚の銅合金からなる外部電極層5を
形成し、積層薄膜コンデンサを得た。
(Example (1)) On the ceramic substrate 1 made of alumina having an average center line roughness (Ra) of 0.5 μm on the surface, the glaze layer 2 (Ra: 0. 005μ
m) is formed thereon, an aluminum film having a thickness of 0.05 μm is formed as the internal electrode layer 3 by a vacuum vapor deposition method, and an aromatic polyimide thin film having a thickness of 0.4 μm is formed as a dielectric layer 4 by a vapor deposition polymerization method. After alternately stacking 15 layers, a protective film 5 made of silicon nitride was formed, and further an external electrode layer 5 made of a copper alloy having a thickness of 25 μm was formed by a low pressure plasma spraying method to obtain a laminated thin film capacitor.

(実施例(2)) 表面の平均中心線粗さ(Ra)が1.0μmのアルミナ
からなるセラミック基板1上に、セラミック基板1の両
端部を除いて40μm厚のグレーズ層2(Ra:0.0
06μm)を形成した後、その上に内部電極層3として
真空蒸着法にて膜厚0.15μmのニッケル膜を、誘電
体層4として蒸着重合法により膜厚0.4μmの芳香族
ポリイミド薄膜を、交互に15層積層した後、窒化シリ
コンからなる保護膜5を形成し、さらに減圧プラズマ溶
射法によって45μm厚のニッケル合金からなる外部電
極層6を形成し、積層薄膜コンデンサを得た。
(Example (2)) On the ceramic substrate 1 made of alumina whose surface has an average centerline roughness (Ra) of 1.0 μm, the glaze layer 2 (Ra: 0) having a thickness of 40 μm except for both ends of the ceramic substrate 1 is formed. .0
06 μm), a nickel film having a film thickness of 0.15 μm is formed thereon as an internal electrode layer 3 by a vacuum vapor deposition method, and an aromatic polyimide thin film having a film thickness of 0.4 μm is formed as a dielectric layer 4 by a vapor deposition polymerization method. After alternately stacking 15 layers, a protective film 5 made of silicon nitride was formed, and further an external electrode layer 6 made of a nickel alloy having a thickness of 45 μm was formed by a low pressure plasma spraying method to obtain a laminated thin film capacitor.

(比較例(1)) 表面の平均中心線粗さ(Ra)が0.5μmのアルミナ
からなるセラミック基板1上に、内部電極層3として真
空蒸着法にて膜厚0.05μmのアルミニウム膜を、誘
電体層4として蒸着重合法により膜厚0.4μmの芳香
族ポリイミド薄膜を、交互に15層積層した後、窒化シ
リコンからなる保護膜5を形成し、さらに減圧プラズマ
溶射法によって25μm厚の銅合金からなる外部電極層
6を形成し、積層薄膜コンデンサを得た。
(Comparative Example (1)) An aluminum film having a thickness of 0.05 μm was formed as an internal electrode layer 3 by a vacuum deposition method on a ceramic substrate 1 made of alumina having an average center line roughness (Ra) of 0.5 μm on the surface. As the dielectric layer 4, 15 layers of an aromatic polyimide thin film having a thickness of 0.4 μm are alternately laminated by a vapor deposition polymerization method, then a protective film 5 made of silicon nitride is formed, and further, a 25 μm thick film is formed by a low pressure plasma spraying method. The external electrode layer 6 made of a copper alloy was formed to obtain a laminated thin film capacitor.

(比較例(2)) 表面の平均中心線粗さ(Ra)が1.0μmのアルミナ
からなるセラミック基板1上に、セラミック基板1の両
端部を除いて10μm厚のグレーズ層2(Ra:0.0
25μm)を形成した後、その上に内部電極層3として
真空蒸着法にて膜厚0.15μmのニッケル膜を、誘電
体層4として蒸着重合法により膜厚0.4μmの芳香族
ポリイミド薄膜を、交互に15層積層した後、窒化シリ
コンからなる保護膜5を形成し、さらに減圧プラズマ溶
射法によって45μm厚のニッケル合金からなる外部電
極層6を形成し、積層薄膜コンデンサを得た。
(Comparative Example (2)) On the ceramic substrate 1 made of alumina whose surface has an average centerline roughness (Ra) of 1.0 μm, the glaze layer 2 (Ra: 0) having a thickness of 10 μm except for both ends of the ceramic substrate 1 is formed. .0
25 μm), a nickel film having a film thickness of 0.15 μm is formed as the internal electrode layer 3 by a vacuum evaporation method, and an aromatic polyimide thin film having a film thickness of 0.4 μm is formed as a dielectric layer 4 by a vapor deposition polymerization method. After alternately stacking 15 layers, a protective film 5 made of silicon nitride was formed, and further an external electrode layer 6 made of a nickel alloy having a thickness of 45 μm was formed by a low pressure plasma spraying method to obtain a laminated thin film capacitor.

(比較例(3)) 表面の平均中心線粗さ(Ra)が1.0μmのアルミナ
からなるセラミック基板1上全面に40μm厚のグレー
ズ層2(Ra:0.006μm)を形成した後、その上
に内部電極層3として真空蒸着法にて膜厚0.15μm
のニッケル膜を、誘電体層4として蒸着重合法により膜
厚0.4μmの芳香族ポリイミド薄膜を、交互に15層
積層した後、窒化シリコンからなる保護膜5を形成し、
さらに減圧プラズマ溶射法によって45μm厚のニッケ
ル合金からなる外部電極層6を形成し、積層薄膜コンデ
ンサを得た。
(Comparative Example (3)) A 40 μm-thick glaze layer 2 (Ra: 0.006 μm) was formed on the entire surface of a ceramic substrate 1 made of alumina having an average centerline roughness (Ra) of 1.0 μm on the surface, and then the The inner electrode layer 3 has a film thickness of 0.15 μm formed thereon by a vacuum deposition method.
As the dielectric layer 4, the nickel film of No. 3 was alternately laminated with an aromatic polyimide thin film having a thickness of 0.4 μm by a vapor deposition polymerization method, and then a protective film 5 made of silicon nitride was formed.
Further, an external electrode layer 6 made of a nickel alloy having a thickness of 45 μm was formed by a low pressure plasma spraying method to obtain a laminated thin film capacitor.

上記の実施例,比較例の積層薄膜コンデンサについて、
V−I特性を比較した結果、実施例(1),(2)および比較
例(3)の積層薄膜コンデンサではリークによるスパイク
ノイズはまったく見られず、安定したV−I特性を示し
た。このときの耐電圧の値は約250V/μmであっ
た。これに対して、比較例2の積層薄膜コンデンサで
は、グレーズ層2の厚みが薄いので、セラミック基板1
の表面粗さの影響を受けて耐電圧が低下し、約150V
/μmとなった。また、比較例(1)の積層薄膜コンデン
サではセラミック基板1の表面粗さの影響を大きく受け
て、セラミック基板1の突起部からのリークによるスパ
イクノイズが低電圧領域から多発し、コンデンサとして
必要な耐電圧特性を得ることができなかった。
Regarding the multilayer thin film capacitors of the above Examples and Comparative Examples,
As a result of comparing the VI characteristics, spike noise due to leakage was not observed at all in the laminated thin film capacitors of Examples (1) and (2) and Comparative Example (3), and stable VI characteristics were exhibited. The withstand voltage value at this time was about 250 V / μm. On the other hand, in the multilayer thin film capacitor of Comparative Example 2, since the glaze layer 2 is thin, the ceramic substrate 1
The withstand voltage drops due to the surface roughness of the
/ Μm. Further, in the multilayer thin film capacitor of Comparative Example (1), the surface roughness of the ceramic substrate 1 is greatly affected, and spike noise due to leakage from the protrusions of the ceramic substrate 1 frequently occurs in the low voltage region. It was not possible to obtain withstand voltage characteristics.

また、上記の実施例,比較例の積層薄膜コンデンサにつ
いて、外部電極のセラミック基板1への付着強度を比較
した結果、実施例(1)および(2)、比較例(1)および(2)の
積層薄膜コンデンサでは、減圧プラズマ溶射法によって
形成された外部電極層の付着強度は10kgf/cm2以上
あり、良好であったのに対して、セラミック基板1全面
にグレーズ層2を形成した比較例(3)の積層薄膜コンデ
ンサでは、グレーズ層2上に減圧プラズマ溶射法によっ
て形成された外部電極層6の付着強度が大幅に低下し、
最低値が1kgf/cm2以下となり、剥離が多発すること
からコンデンサとして必要なレベルを満足していない。
In addition, as a result of comparing the adhesion strength of the external electrodes to the ceramic substrate 1 of the multilayer thin film capacitors of the above-mentioned Examples and Comparative Examples, it was found that the results of Examples (1) and (2) and Comparative Examples (1) and (2) In the laminated thin film capacitor, the adhesion strength of the external electrode layer formed by the low pressure plasma spraying method was 10 kgf / cm 2 or more, which was good, while the comparative example in which the glaze layer 2 was formed on the entire surface of the ceramic substrate 1 ( In the multilayer thin film capacitor of 3), the adhesion strength of the external electrode layer 6 formed on the glaze layer 2 by the low pressure plasma spraying method is significantly reduced,
The minimum value is less than 1 kgf / cm 2 , and peeling occurs frequently, so it does not satisfy the level required as a capacitor.

なお、本実施例では、セラミック基板1の一主面にグレ
ーズ層2を設けた場合について述べたが、両主面にグレ
ーズ層を形成し、両主面に積層薄膜コンデンサを形成す
る場合にも本発明は適用できる。
In this embodiment, the case where the glaze layer 2 is provided on one main surface of the ceramic substrate 1 has been described, but also when the glaze layers are formed on both main surfaces and the laminated thin film capacitor is formed on both main surfaces. The present invention can be applied.

発明の効果 以上の実施例から明らかなように本発明によれば、少な
くとも一主面上の両端部を除く領域にグレーズ層を形成
したセラミック基板と、グレーズ層上に誘電体層を間に
介在させて積層され各一端がグレーズ層を越えてセラミ
ック基板の両端部に一層毎交互に延長して配設された一
対の内部電極層と、積層された一対の内部電極層および
誘電体層上にセラミック基板の両端部を除いて形成され
た保護膜とその保護膜により被覆されていない内部電極
層の延長部分のセラミック基板の両端部に形成された外
部電極層とを有する構成よりなるので、高耐圧を有し、
小形,軽量,低コストで、高品質の積層薄膜コンデンサ
を提供できる。
EFFECTS OF THE INVENTION As is apparent from the above-described embodiments, according to the present invention, a ceramic substrate having a glaze layer formed on at least one main surface except for both ends, and a dielectric layer interposed between the ceramic substrate and the glaze layer. A pair of internal electrode layers that are laminated by alternately extending over the glaze layer at both ends of the ceramic substrate, and a pair of internal electrode layers and a dielectric layer that are laminated. Since the protective film is formed excluding both end portions of the ceramic substrate and the external electrode layers formed on both end portions of the ceramic substrate of the extended portion of the internal electrode layer not covered by the protective film, Withstand voltage,
It is possible to provide high quality multilayer thin film capacitors that are compact, lightweight and low cost.

【図面の簡単な説明】 第1図は本発明の一実施例の積層薄膜コンデンサの断面
図である。 1……セラミック基板、2……グレーズ層、3……内部
電極層、4……誘電体層、5……保護膜、6……外部電
極層。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a multilayer thin film capacitor of one embodiment of the present invention. 1 ... Ceramic substrate, 2 ... Glaze layer, 3 ... Internal electrode layer, 4 ... Dielectric layer, 5 ... Protective film, 6 ... External electrode layer.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】少なくとも一主面上の両端部を除く領域に
グレーズ層を形成したセラミック基板と、 前記グレーズ層上に誘電体層を間に介在させて積層され
各一端が前記グレーズ層を越えて前記セラミック基板の
両端部に一層毎交互に延長して配設された一対の内部電
極層と、前記積層された一対の内部電極層および誘電体
層上に前記セラミック基板の両端部を除いて形成された
保護膜と その保護膜により被覆されていない前記内部電極層の延
長部分の前記セラミック基板の両端部に形成された外部
電極層と を有する積層薄膜コンデンサ。
1. A ceramic substrate having a glaze layer formed on at least one main surface except for both ends thereof, and a ceramic substrate laminated on the glaze layer with a dielectric layer interposed therebetween, and one end of the ceramic substrate exceeds the glaze layer. A pair of internal electrode layers that are alternately extended and arranged on both ends of the ceramic substrate, and both ends of the ceramic substrate are removed on the laminated pair of internal electrode layers and dielectric layers. A multilayer thin film capacitor having a formed protective film and external electrode layers formed on both ends of the ceramic substrate in an extended portion of the internal electrode layer not covered by the protective film.
【請求項2】グレーズ層の表面の平均中心線粗さが0.
01μm以下である請求項(1)記載の積層薄膜コンデン
サ。
2. The average centerline roughness of the surface of the glaze layer is 0.
The multilayer thin film capacitor according to claim 1, which has a thickness of 01 μm or less.
【請求項3】グレーズ層のないセラミック基板の両端部
の平均中心線粗さが0.1μm以上である請求項(1)ま
たは(2)記載の積層薄膜コンデンサ。
3. The multilayer thin film capacitor according to claim 1, wherein the average centerline roughness of both ends of the ceramic substrate having no glaze layer is 0.1 μm or more.
【請求項4】セラミック基板の少なくとも一主面上の両
端部を除く領域にグレーズ層を形成する工程と、 そのグレーズ層上およびグレーズ層のない前記セラミッ
ク基板の両端部のうち一方の端部上にまで一方の内部電
極層を形成し、 前記グレーズ層上に形成された前記内部電極層上に誘電
体層を形成し、 その誘電体層をはさんで前記セラミック基板の両端部の
うち他方の端部上にまで他方の内部電極層を形成し、前
記内部電極層と誘電体層を交互に積層する工程と、 その積層された内部電極層および誘電体層上に前記セラ
ミック基板の両端部を除いて保護膜を形成する工程と、 その保護膜により被覆されていない前記セラミック基板
の両端部上の前記内部電極層上に外部電極層を形成する
工程と を有する積層薄膜コンデンサの製造方法。
4. A step of forming a glaze layer in a region of at least one main surface of the ceramic substrate excluding both end portions, and one end portion of the both ends of the glaze layer and the glaze layer-free ceramic substrate. Up to one internal electrode layer, a dielectric layer is formed on the internal electrode layer formed on the glaze layer, and the other of the both ends of the ceramic substrate is sandwiched across the dielectric layer. Forming the other internal electrode layer up to the end, and alternately laminating the internal electrode layer and the dielectric layer, and placing both ends of the ceramic substrate on the laminated internal electrode layer and dielectric layer. A method of manufacturing a multilayer thin film capacitor, comprising: a step of forming a protective film, and a step of forming external electrode layers on the internal electrode layers on both ends of the ceramic substrate not covered by the protective film.
【請求項5】外部電極層を減圧プラズマ溶射法により形
成する請求項(4)記載の積層薄膜コンデンサの製造方
法。
5. The method of manufacturing a multilayer thin film capacitor according to claim 4, wherein the external electrode layer is formed by a low pressure plasma spraying method.
JP14477690A 1990-06-01 1990-06-01 Multilayer thin film capacitor and manufacturing method thereof Expired - Lifetime JPH0666218B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14477690A JPH0666218B2 (en) 1990-06-01 1990-06-01 Multilayer thin film capacitor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14477690A JPH0666218B2 (en) 1990-06-01 1990-06-01 Multilayer thin film capacitor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0437105A JPH0437105A (en) 1992-02-07
JPH0666218B2 true JPH0666218B2 (en) 1994-08-24

Family

ID=15370169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14477690A Expired - Lifetime JPH0666218B2 (en) 1990-06-01 1990-06-01 Multilayer thin film capacitor and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0666218B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224040B2 (en) * 2003-11-28 2007-05-29 Gennum Corporation Multi-level thin film capacitor on a ceramic substrate
US8569142B2 (en) 2003-11-28 2013-10-29 Blackberry Limited Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same
JP4501077B2 (en) 2006-02-17 2010-07-14 Tdk株式会社 Thin film device

Also Published As

Publication number Publication date
JPH0437105A (en) 1992-02-07

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