JPS6073259U - Dynamic ROM - Google Patents

Dynamic ROM

Info

Publication number
JPS6073259U
JPS6073259U JP16628383U JP16628383U JPS6073259U JP S6073259 U JPS6073259 U JP S6073259U JP 16628383 U JP16628383 U JP 16628383U JP 16628383 U JP16628383 U JP 16628383U JP S6073259 U JPS6073259 U JP S6073259U
Authority
JP
Japan
Prior art keywords
line
mos transistor
address
dynamic
address line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16628383U
Other languages
Japanese (ja)
Other versions
JPH0334922Y2 (en
Inventor
太斎　文博
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP16628383U priority Critical patent/JPS6073259U/en
Publication of JPS6073259U publication Critical patent/JPS6073259U/en
Application granted granted Critical
Publication of JPH0334922Y2 publication Critical patent/JPH0334922Y2/ja
Granted legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はダイナミックＲＯＭの回路図、第２図は第１図
に示されたダイナミックＲＯＭを形成する半導体装置の
従来例を示す断面図、第３図は本考案の実施例を示す断
面図である。 主な図番の説明、２・・・・・・アドレスライン、５゜
８・・・・・・ＭＯＳトランジスタ、６・・・・・・出
力ライン、７・・・・・・電源ライン、１０・・・・・
・線間容量、１１，２１・・・・・・寄生トランジスタ
、１４・・・・・・ソース領域、１５・・・・・・ドレ
イン領域、１６・・・・・・酸化膜、１７・・・・・・
半導体基体、“１８・・・・・・Ｐ型頭域、１９，２０
・・・・・・Ｎ型領域。FIG. 1 is a circuit diagram of a dynamic ROM, FIG. 2 is a sectional view showing a conventional example of a semiconductor device forming the dynamic ROM shown in FIG. 1, and FIG. 3 is a sectional view showing an embodiment of the present invention. be. Explanation of main drawing numbers, 2...address line, 5゜8...MOS transistor, 6...output line, 7...power line, 10・・・・・・
・Line capacitance, 11, 21... Parasitic transistor, 14... Source region, 15... Drain region, 16... Oxide film, 17...・・・・・・
Semiconductor substrate, "18...P-type head area, 19,20
...N-type region.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アドレス信号のデコーダによって選択されるアドレスラ
インと、該アドレスラインに接続されたプリチャージ用
のＭＯＳトランジスタと、前記アドレスラインとマトリ
クスを構成する出力ラインと、前記アドレスラインと出
力ラインの任意の交点に設けられたデータを記憶するた
めのＭＯＳトランジスタとを有するダイナミックＲＯＭ
に於いて、前記プリチャージ用のＭＯＳトランジスタが
形成される半導体領域と、前記出力ライン及び記憶用の
ＭＯＳトランジスタが形成される半導体領域とを分離し
て成るダイナミックＲＯＭ０An address line selected by an address signal decoder, a precharging MOS transistor connected to the address line, an output line forming a matrix with the address line, and an arbitrary intersection between the address line and the output line. A dynamic ROM having a MOS transistor for storing data provided therein.
In the dynamic ROM0, a semiconductor region in which the precharge MOS transistor is formed and a semiconductor region in which the output line and storage MOS transistors are formed are separated.
JP16628383U 1983-10-26 1983-10-26 Dynamic ROM Granted JPS6073259U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16628383U JPS6073259U (en) 1983-10-26 1983-10-26 Dynamic ROM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16628383U JPS6073259U (en) 1983-10-26 1983-10-26 Dynamic ROM

Publications (2)

Publication Number Publication Date
JPS6073259U true JPS6073259U (en) 1985-05-23
JPH0334922Y2 JPH0334922Y2 (en) 1991-07-24

Family

ID=30364073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16628383U Granted JPS6073259U (en) 1983-10-26 1983-10-26 Dynamic ROM

Country Status (1)

Country Link
JP (1) JPS6073259U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5438782A (en) * 1977-09-01 1979-03-23 Nec Corp Production of integrated circuit device
JPS54107278A (en) * 1978-02-10 1979-08-22 Hitachi Ltd Semiconductor device
JPS58116763A (en) * 1982-12-24 1983-07-12 Hitachi Ltd Mos type rom

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5438782A (en) * 1977-09-01 1979-03-23 Nec Corp Production of integrated circuit device
JPS54107278A (en) * 1978-02-10 1979-08-22 Hitachi Ltd Semiconductor device
JPS58116763A (en) * 1982-12-24 1983-07-12 Hitachi Ltd Mos type rom

Also Published As

Publication number Publication date
JPH0334922Y2 (en) 1991-07-24

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