JPS6072228A - Method for inpurity doping into semiconductor substrate - Google Patents

Abstract

PURPOSE:To dope impurities without causing a charge-up and breakage of elements by implanting the ions accelerated electrically into a semiconductor substrate after neutralizing the ions by an electron current, followed by annealing by a high-temperature furnace, irradiation with a high-energy beam, heating by a lamp and etc. CONSTITUTION:A p type Si substrate 1 is coated with an SiO2 film 2 and it is etched with using a resist film 3 of the predetermined size as a mask to open the desired apertures 4a and 4b. Next, on the substrate exposed in the apertures 4a and 4b, impurity doped layers 5a and 5b are formed by use of a neutral beam. At this time, the neutral beam is As<+> ion accelerated with 40keV which is then neutralized by an electron current on a way to the substrate. After that, the film 3 is removed and an SiO2 film 6 and a PSG film 7 are deposited with lamination over the whole surface. Then the substrate is subjected a heat treatment at 800-1,000 deg.C to make the layers 5a and 5b into n<+> type shallow source and drain regions 8a and 8b.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a method of doping impurities into a semiconductor substrate,
In particular, electrically neutralized impurity particles are implanted into a single crystal semiconductor substrate or semiconductor thin film.

The present invention relates to a method of doping impurities such as arsenic, boronic, and phosphorous through an annealing process while preventing electrical charge-up.

[Prior art and its problems]

As is well known (in the manufacture of a semiconductor device 1, for example, an MO8 field effect transistor, impurities are doped into a semiconductor substrate (hereinafter referred to as a silicon substrate),
A step of forming a drain region is essential. Furthermore, in the manufacture of elements such as diodes and bipolar transistors, it is essential to form p-N junctions by doping with impurities.

Traditionally, methods for doping these impurities include ion implantation, addition using a glass layer or silicon layer containing impurities (so-called doped oxide method or doped silicon method), or diffusion from the gas phase in a high-temperature heat treatment furnace. The first prize is known. Among these, the viewpoints of high integration and high speed of elements, ease of process control,
From the viewpoint of commercialization, ion implantation is considered to be the most suitable impurity doping method.

However, in the ion implantation method, since ions are charged particles, charge-up and dielectric breakdown occur during ion implantation, especially on the sample surface. In particular, as the degree of integration of devices increases and speeds increase, the gate insulating film of MO81 transistors, for example, has a thickness of less than 200 Å, making dielectric breakdown more likely to occur. In addition, the planar gate length is smaller than 1 μm, and from this point of view it can be said that dielectric breakdown is extremely likely to occur. Under these circumstances, high-dose ion implantation must be performed with extreme caution. It is expected that problems such as charge-up and dielectric breakdown will become more serious as the dimensions of elements become smaller in the future.

[Purpose of the invention]

The present invention has been made in view of this point.

An object of the present invention is to provide a method for doping impurities without causing a charge atom or dielectric breakdown of an element by using an uncharged neutral beam as an impurity and injecting the beam into a semiconductor substrate. purpose.

[Summary of the invention] In the present invention, impurities are first ionized in advance, and kinetic energy is given by accelerating them using an electric field.
) to neutralize the ions, and this neutral beam is implanted into the semiconductor substrate, followed by high temperature treatment and beam annealing.
This method is used to dope impurities by annealing, for example, to form PN junctions, such as source and drain regions of MOS transistors.

〔Effect of the invention〕

According to the present invention, it has become possible to fabricate ultra-high density integrated circuits by forming elements such as transistor diodes and capacitors with ultra-fine patterns with high reproducibility (and precision) and connecting them with wiring patterns. The effects of the present invention are particularly noticeable in devices such as SOS devices in which individual elements are electrically completely isolated.

[Embodiments of the invention]

Examples of the present invention will be described below. First, shallow p, n
, q5 will be explained using the drawings.

[Example 1] FIG. 1 (al is 1, for example, an oxide film 2 is formed to a thickness of about 3000× on the -1 side of a p-type silicon substrate 1 having a specific resistance of about 10 Ω-cm, Using the resist 3 as a mask, a predetermined n-formation area l is formed with an opening 4'.
-a and 4b are drilled. Next, Figure 1 (
As shown in b), impurity implantation layers 5 a , 5 b are formed in the silicon substrate exposed through the openings 4 a and 4 b using the neutral beam according to the present invention. In this neutral beam, arsenic ions are accelerated at 40 KeV in advance and are neutralized by an electron flow as they are guided to the silicon substrate, and the range is almost the same as that of 40 KeV ion implantation. . Neutral beam do, <l
IT directs part of the ion beam to a target other than the silicon substrate.

It can be determined by monitoring this current value.

Further, although the oxide film 2 alone is sufficient as an implantation mask during neutral beam irradiation, the resist 3 can also be used as a mask at the same time. Next, after peeling off the resist 3, as shown in FIG.
are deposited in layers. And the total of these is 800 to 10
When heat-treated at a temperature of 00°C, shallow, high-concentration n layers 8a and 8b are obtained, as shown in Figure 1 (dl).
The layer is formed by the subsequent process (the process shown in the figure), for example, MOS.
Used as the source and drain of a transistor.

An important feature of the present invention is an impurity doping method that takes advantage of the advantages of ion implantation while preventing charge-up and device dielectric breakdown. Therefore, impurity introduction has a directionality, and during high-temperature heat treatment after impurity introduction, a lateral diffusion bed along the substrate surface (the impurity wraps around under the oxide film mask in Figure 1 of the above example). ) is considerably suppressed.

This is extremely convenient when aiming for miniaturization and higher density of integrated circuit elements. Also, controllability of impurity concentration,
Needless to say, the uniformity is good because the characteristics of ion implantation are utilized as they are.

Furthermore, if the heat treatment after neutral beam irradiation is performed in an oxidizing atmosphere, the segregation effect of arsenic impurities at the oxide-silicon substrate interface can be utilized when arsenic in silicone is diffused.

Further, as another practical example of the present invention, a method for manufacturing an npnl transistor will be taken up, and an embodiment in which the features of the present invention are utilized in a method for forming an n-arsenic buried layer will be described with reference to one drawing.

[Example 2] In FIG. 2, first, a silicon oxide film 22 acting as a diffusion prevention mask is deposited on the entire surface of a mirror-polished p-type silicon substrate 21 having a specific resistance of, for example, 20 Ω-cm. The resist 23 is used as a mask to form an opening 24 in a predetermined diffusion region using a well-known photolithography method. Next, a shallow (for example, 400 A or less) high concentration (for example, 3 x 10 "7 cm or more n+ with arsenic) A25 is formed on the surface of the silicon substrate exposed by the opening 24. At this time, a neutral beam The same as in the previous embodiment, an ion beam accelerated to 40 KeV and neutralized by electron flow is used. Also, the resist 23 may be omitted during the neutral beam implantation.

Next, after peeling off the resist 23, a silicon oxide film 24 is formed to a thickness of about 100 OA for the purpose of preventing out-dlffusion of arsenic impurities, and is heat-treated in a nurturing atmosphere to form an n+ collector buried layer. Fbl forming 27. Subsequently, the silicon oxide films 26 and 2
2, etc. to expose a clean and smooth epitaxial target surface 28 (C1 degree ζ), an n-type silicon epitaxial layer 29 is formed on the epitaxial target surface 28 (di. At this time, the buried layer 27 also permeates and diffuses into the epitaxial layer, forming the buried layer 30 again.

Thereafter, a p++ diffusion isolation layer 31 is used to electrically isolate the transistor from other elements or circuits in the epitaxial layer.
a to 31b, collector extraction n+ type scattering layer 32, p type base region 33, n++ emitter region 34. Silicon surface protection insulating film 35, also used as a diffusion mask. A tel forming an npn transistor including electrodes 36a to 36dτ and the like.

In the above embodiment, arsenic impurities are introduced into silicon.
In the case of collector formationζAs mentioned above, as with arsenic,
The present invention can also be applied to the case of forming an n buried layer using antimony impurity having a small thermal diffusion coefficient in silicon. Furthermore, although the above embodiments have been described with respect to forming a buried layer in one selected region, the present invention may also be applied to the manufacture of a semiconductor device that includes a step of forming an n+ layer over the entire surface of a substrate, for example.

The present invention can be applied. Furthermore, it is possible to form a -p buried layer of an npn transistor, or to add p+ to the entire surface of a substrate.
The above embodiments can also be modified and applied to the manufacturing of a semiconductor device including a step of forming a layer and providing a semiconductor film thereon. In addition, as in the embodiment, not only impurities that have the opposite conductivity type to the substrate, but also impurities that give the same conductivity type as the substrate, are added to a predetermined region of the main surface of the substrate or to the entire main surface of the substrate. The present invention can be appropriately modified and applied to the case of manufacturing a semiconductor device including a step of performing beam injection and then forming a semiconductor film on the main surface.

[Brief explanation of drawings]

FIG. 1 (al~(dl) is a sectional view of the manufacturing process of one embodiment of the present invention, and FIG. 2 (al~(el) is a sectional view of the manufacturing process of another embodiment of the invention. In the figures. 21... Silicon substrate, 2.22... Silicon oxide film, 5a, 5b, 25... Impurity implantation layer, 6°2
6... Silicon oxide film, 7... Phosphorus glass layer, 8a
. 8b...n layer, 29... epitaxial layer, 30
...n+ buried layer, 31a, 31b...p++ dispersion layer, 32...n collector region, 33...p
Pace area, 34...n+ emitter area, 35...
Surface protection insulating film, 36a to 36d...electrode. Representative patent attorney Kensuke Chika (and 1 other person) Figure 1 (-J) CC) (d) Figure 2 (θ7)

Claims (1)

[Claims] A semiconductor substrate characterized by a step of injecting electrically accelerated ions into a semiconductor substrate after neutralizing them through an electron flow, and then annealing them in a high-temperature furnace, high-energy beam irradiation, lamp heating, etc. impurity doping method.