JPS607143A - Method of evaluation of silicon wafer - Google Patents

Abstract

PURPOSE:To evaluate a thermal oxide film and evaluate the density of micro- defects easily and rapidly with a large area by a method wherein the condition for the formation of an MOS capacitor and that for the measurement of insulation breakdown withstand voltage are made constant. CONSTITUTION:An Si oxide film 2 is formed on an Si wafer 1 doped with an impurity such as phosphorus or boron by a thermal oxidation method. At the time of this thermal oxidation, the micro defects in the Si are taken in the oxidation, resulting in the formation of metallic electrodes 3 on the film 2. The insulation breakdown withstand voltage of a plurality of the MOS capacitors formed thereby is measured, and the capacitors of no breakdown are removed, further the initial short-circuit is removed because of being caused by surface contamination before the thermal oxidation. Then, the Si wafer is evaluated on the basis of the ratio of the number of remaining samples to the number of all the measured samples. The Si wafer can be evaluated by a method wherein the condition for the formation of the MOS capacitor and that for the measurement of insulation breakdown withstand voltage are made constant with respect to various kind of Si wafers.

Description

Detailed Description of the Invention [Technical field to which the invention pertains] The present invention relates to a method for evaluating minute defects existing near the surface of a Si wafer, and in particular to a method for evaluating micro defects existing in the vicinity of the surface of a Si wafer. Regarding evaluation methods.

[Prior art and its problems]

Recently, the density of semiconductor integrated circuits has increased significantly, and there are extremely strict requirements for reducing defects in a clean thermal oxide film.

Conventionally, defects in silicon thermal oxide films have been caused by contamination on the surface of the silicon wafer before the thermal oxide film is formed. However, the water used for wafer cleaning, acid, alkali,
Advances in filter technology have made it possible to significantly reduce the amount of bacteria and particulates in organic chemicals. In addition, dust in the air can be reduced by maintaining clean rooms and improving clean benches, and the problem of surface contamination of silicon wafers can now be largely solved. However, at the same time as the problem of surface contamination was solved, it became clear that the cause of defects in the silicon thermal oxide film was present in the Si wafer.

If defects in St that become oxide film defects are uniformly distributed in Si, the number of defects in Si that are incorporated into the oxide film by thermal oxidation increases in proportion to the thickness of the oxide film. As a result, oxide film defects with a finite breakdown voltage increase with film thickness;
The insulation defect rate of a MOS capacitor formed by providing an electrode on an oxide film also increases with the film thickness, as shown in FIG.

Conventionally, direct observation using a transmission electron microscope (TanN), measurement of minority carrier lifetime, etc. have been used to evaluate defects in S1, but TE
In the case of M, the thermal oxide film of Si has a 50%
It is extremely difficult to observe micro defects smaller than A.

Furthermore, in the case of a St wafer that has not been heat-treated, its defect density is below Q9c7rL"", which is
It is nearly impossible to observe with EM and evaluate the St wafer based on the number. Furthermore, when measuring the lifetime of minority carriers using light or sound waves, the average value of %St for the entire wafer is evaluated, which is not suitable for evaluating the vicinity of the surface, which is a problem in integrated circuits. In addition, in the evaluation by lifetime measurement from a deep depletion state to an inverted state in a MOS capacitor using a gate insulating film for a Si thermal oxide film, it is difficult to remove the influence of the St interface, etc., or there are problems such as dependence on measurement conditions. Due to this problem, it is not suitable for evaluating micro defects of 50X or less.

[Objective of the Invention] The present invention has been made in view of these points, and is capable of evaluating the thermal oxide film itself, which is intended to reduce micro defects in St wafers, and is capable of reducing the density of micro defects over a large area. The purpose is to provide a method that can be evaluated easily and quickly.

[Summary of the invention]

In the present invention, a silicon oxide film is formed by a thermal oxidation method on an S1 wafer doped with impurities such as phosphorus or boron.

During thermal oxidation, minute defects in Si are incorporated into the oxidation.

A metal electrode is formed on the silicon oxide film. The dielectric breakdown voltage of a plurality of MOS capacitors formed by the above process is measured, and unbroken ones are removed, and initial short circuits due to surface contamination before thermal oxidation are removed. The St wafer is evaluated based on the ratio of the number of remaining samples to the total number of measurement samples. MOS capacitor formation conditions (e.g., oxidation method, oxide film thickness, electrode shape, material, etc.) and dielectric breakdown voltage measurement conditions (e.g., voltage rise rate, dielectric breakdown judgment current, etc.) are determined for each S1 wafer. By keeping St
Wafers can be evaluated.

〔Effect of the invention〕

According to the present invention, defects in silicon that are difficult to find using a transmission electron microscope can be easily and quickly evaluated over a large area using the practical item of oxide film breakdown voltage. Further, by using an oxide film thickness that corresponds to the specifications of the silicon wafer to be used, it is possible to improve the silicon wafer without excessive specifications.

[Embodiments of the invention]

Below are five examples of applying the present invention to the evaluation of St wafers manufactured by the Czochralski (CZ) method.
This will be explained using drawings. FIG. 2 shows a cross-sectional view of the sample. First, the P-type St wafer 1 to be evaluated is heated at 100°
A 400X oxide film 2 is formed in C dry oxygen. Subsequently, a polycrystalline silicon film 3 having a thickness of about 600 OA is formed on the thermal oxide film. Further, phosphorus is diffused into the polycrystalline silicon 3 to lower the resistance, and the polycrystalline silicon is selectively etched by photolithography. FIG. 3 is a conceptual diagram showing a method for measuring the dielectric breakdown voltage of the sample shown in FIG. 2. 4 is a resistor, 5 is a voltmeter, and 6 is a power source. The voltage applied to the gate electrode is increased at a rate of 2 MV/cIrL per second or higher to a value that forms a majority carrier accumulation layer on the surface of the 81 substrate. For example, I in series with the sample 11 and the power supply.
A resistor of MΩ is connected, and the voltage drop across the resistor is successively monitored, and the voltage at which the current becomes 0.1 μA is measured as the withstand voltage.

FIG. 4 is a withstand voltage histogram showing frequency with respect to withstand voltage. Since MOS capacitors with a breakdown voltage of 8M/crrL or less contain defects, the defective rate with a breakdown voltage of 8MV/ffi or less for all measurements on one wafer is calculated as F.
If the defect distribution is Boannon distribution, then
The defect density ρ is calculated by ρ. However, the gate area A has a defective rate F of 50
It is necessary to select ρ so that it is less than or equal to ρ, otherwise ρ will have a large error. ρ obtained by the above
The defect density ρ81 at 81 is calculated as ρ sl αtox α 2,2 (volume increase rate when changing from St to 5tO2). The crystal quality of the 81 surface can be evaluated based on the value of ρ81.

As for the Si wafer to be evaluated, we used the original Sl wafer delivered by the wafer manufacturer and the 110% Si wafer before gate oxidation.
When using St Ueno® heat-treated for 0'01 hours, the former is ρ5i = 4 × 10 (crfL ), and the latter is /j8i =
5×10 5 (C11L-3), which indicates that the high temperature heat treatment before gate oxidation reduces the number of defects in Si that become oxide film defects.

In the above embodiments, p-type Si was used, but the substrate S
The conductivity type of t does not matter. Further, the resistance is also not limited as long as it is not so high as to cause a problem in voltage drop across the St substrate, such as several hundreds of ohms. There is no problem with the electrode as long as it is free from contamination and does not change the withstand voltage of the thermal oxide film.

It goes without saying that other changes can be made in accordance with the spirit of the present invention.

[Brief explanation of drawings]

Fig. 1 is a characteristic diagram showing the dependence of the insulation defect rate of a MOS capacitor on oxide film thickness, Fig. 2 is a cross-sectional view showing an example of a MOS capacitor, and Fig. 3 is a diagram showing an example of a circuit used for silicon evaluation. FIG. 4 is a characteristic diagram showing the relationship between dielectric breakdown voltage and insulation failure frequency of a MOS capacitor. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Social-relationship, broken blood (H-style)

Claims (1)

[Claims] After forming a silicon wafer by thermal oxidation on a silicon wafer doped with impurities, an electrode film is formed on the silicon oxide film, and the dielectric breakdown voltage of the MOS capacitor formed by the above process is measured. A silicon wafer d measurement method characterized by making a determination based on a failure rate with withstand voltage.