JP2001213694A - Semiconductor wafer with low copper content - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer which has lower copper content, higher device property, and higher yield in device manufacturing. SOLUTION: The copper contained in the silicon wafer is diffused by heating the wafer 400 deg.C, collected on the wafer surface, dissolved in the fluoric acid containing recovery liquid dropped on the wafer surface, and removed from the surface. Therefore, the copper content in the wafer is reduced to 1.1×1011cm-2 or less. As a result, the higher device property is obtained and yield in device manufacturing is heightened. Adopting the copper content reducing method based on the LTD method, the semiconductor wafer with lower copper density, 1.1×1011cm-2 or less, can be efficiently produced in high yield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low copper concentration semiconductor wafer, and more particularly, to a low copper concentration semiconductor wafer having a low concentration of copper on the surface and inside of the semiconductor wafer and having high device characteristics.

[0002]

2. Description of the Related Art It has been known that copper existing on the surface of a silicon wafer affects the gate oxide film breakdown voltage. However, there was no knowledge as to whether or not copper existing inside the silicon wafer affected the gate oxide film breakdown voltage. Further, a method of measuring the concentration of copper inside a silicon wafer with high sensitivity has not been known. Therefore, as disclosed in Japanese Patent Application Laid-Open No. 9-64133, a method for measuring the concentration of copper present inside a silicon wafer has been proposed by the present applicant. This is L
TD (Low Temperature Diffuse)
ion) method. In the LTD method, a semiconductor wafer is heated to several hundred degrees Celsius to diffuse copper inside the wafer, and copper existing inside the wafer is collected on the wafer surface. Thereafter, a small amount of a recovery solution composed of an HF solution or a mixed solution of HF / H ₂ O ₂ is dropped on the wafer surface, and copper collected on the wafer surface is dissolved and recovered in the recovery solution. Then, the recovered liquid is analyzed by TXRF (total reflection X-ray fluorescence analysis) or AAS (atomic absorption analysis) to measure the amount of copper in the recovered liquid.

[0003]

SUMMARY OF THE INVENTION Then, the inventor sets L
When the relationship between the concentration of copper present inside and on the surface of the silicon wafer detected by the TD method and the breakdown voltage of the gate oxide film was examined, it was found that there was a good correlation between these. Further, according to the LTD method, it is possible to accurately measure the concentration of copper not only on the surface of the wafer but also on the inside thereof, and to judge the quality of the silicon wafer by using the measured value of the copper concentration. It was found that it was possible to do. Based on such knowledge, the inventor has completed the present invention.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a low-copper-concentration semiconductor wafer capable of obtaining high device characteristics and a high yield in device fabrication.

[0005]

According to the first aspect of the present invention, there is provided a low-concentration semiconductor wafer having a copper concentration of 1.1 × 10 ¹¹ cm ⁻² or less when a semiconductor wafer is measured by an LTD method. It is. The type of the target semiconductor wafer is not limited. For example, silicon wafers, bonded wafers, SOI (Silicon on Insu)
Later wafers and epitaxial wafers may be used. The method for producing a semiconductor wafer having a copper concentration of 1.1 × 10 ¹¹ cm ⁻² or less is not limited. In short, when the copper concentration of the semiconductor wafer is measured by the LTD method, the value may be 1.1 × 10 ¹¹ cm ⁻² or less. 1.1 ×
The reason for ^setting it to 10 ¹¹ cm ⁻² or less is as follows. That is, when judging the pass or fail of the wafer,
In particular, when a CMOS device is included, it is generally performed based on the yield rate of the oxide film breakdown voltage.
Since the pass / fail judgment of the non-defective product ratio of the oxide film breakdown voltage differs depending on the target device, it cannot be uniquely determined. Here, 75%, which is generally regarded as a passing line for a non-defective product rate of 100%, is used as a pass / fail judgment criterion. If the density is 1.1 × 10 ¹¹ cm ⁻² or less, the yield rate exceeds 75%.

According to a second aspect of the present invention, the semiconductor wafer is a mirror-polished silicon wafer.
2. The low copper concentration semiconductor wafer described in 1. above. Devices are formed on the mirror-polished wafer.

According to a third aspect of the present invention, there is provided the low copper concentration semiconductor wafer according to the first aspect, wherein the semiconductor wafer is an SOI wafer. As a method for manufacturing the SOI wafer, any of a bonding method, a SIMOX method, and the like may be used.

According to a fourth aspect of the invention, there is provided the low copper concentration semiconductor wafer according to the first aspect, wherein the semiconductor wafer is an epitaxial wafer.

[0009]

According to the present invention, the concentration of copper contained in the surface of a semiconductor wafer and the inside thereof is 1.1 × 10 ¹¹ c
Since m ^-2 or less and low, for example, this making the device of the CMOS structure on the surface of a semiconductor wafer, an inconvenience such as eliminating degrade the oxide dielectric breakdown voltage of the gate oxide film of copper enters the gate oxide film. As a result, the device formed on the semiconductor wafer has high device characteristics, and can increase the yield of device fabrication.
Further, if the LTD method is used, it is possible to accurately measure the amount of copper contamination in each step (etching, polishing, oxidation, diffusion, and the like) in a silicon wafer manufacturing process. As a result, the contamination source can be specified, and the contamination due to the change in the process conditions can be reduced. In addition, it is possible to specifically determine whether or not a change in equipment used in each step causes copper contamination and the degree of the influence.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flow sheet showing an LTD method for measuring the concentration of copper on the surface and inside of a semiconductor wafer according to one embodiment of the present invention. Figure 2 shows LT
It is a graph which shows the collection rate of copper by the D method. First, FIG.
The LTD method will be described with reference to FIG. First, a silicon wafer PW having copper contamination in the bulk is prepared. This silicon wafer is placed on a clean silicon wafer with its mirror side (front side) facing up. This clean silicon wafer is assumed to be mounted on a hot plate (the surface is made of ceramics). When the silicon wafer is a P-type, heating is performed at 400 ° C. for 30 minutes in the air. In the case of N-type, heating is performed at 400 ° C. for one hour. This heat treatment is performed in a clean room that does not contaminate the wafer. The silicon wafer may be heated in a heat treatment furnace instead of the hot plate. In this case, in the atmosphere, N
Heating is performed in a ₂ / O ₂ gas or Ar / O ₂ gas atmosphere. As a result of this heat treatment, most of the copper in the bulk moves to the front and back sides by diffusion, respectively. In particular, 80% or more of the copper moves to the surface side. Next, HF (2%) or HF (2%) / H ₂ O ₂ (2
%) The mixed solution is dropped by 100 to 200 μl, and copper on the surface and in the vicinity thereof is recovered with the recovered liquid. That is,
The copper droplets collected on the surface of the wafer are dissolved in the liquid by moving the collected droplets, which have been dropped on the surface of the wafer, so as to roll, and are collected. In addition,
Copper on the back side can also be recovered by the same method.

As shown in FIG. 2, 2%
In the case of recovery using an HF solution or an HF (2%) / H ₂ O ₂ (2%) solution, the recovery rate of copper from the wafer surface is approximately 100%. It is clear that the recovery rate is extremely high as compared with the case where low-temperature heating is not performed.

[0012]

[Table 1]

Table 1 shows the oxide film breakdown voltage non-defective rate of the low copper concentration silicon wafer according to the present invention, in which the copper concentration was measured based on the LTD method, together with comparative examples. The oxide film breakdown voltage non-defective rate is determined based on the test data of the oxide film breakdown voltage of the gate oxide film formed on the silicon wafer according to the example.
In Example 1 and Comparative Examples 1 and 2, a bonded SOI wafer was used as a sample wafer, and in Example 2 and Comparative Example 4, a mirror-finished silicon wafer was used. Comparative Example 3 and Example 3 are both cases where a P-type epitaxial layer having a resistance value of 10 Ωcm was grown on a P ⁻ wafer by 10 μm. Comparative Example 3
Since copper contamination occurred after the epitaxial process,
The non-defective product with an oxide film withstand voltage of 9.4% was low, and no copper contamination was observed in Example 3, so that the non-defective product with an oxide film withstand voltage was 98.6%.
And higher. Comparative Example 4 has a higher Cu concentration than Example 2 and deteriorates the yield rate. The process where Cu contamination occurs is a polishing process. Details of the bonded SOI wafer are as follows. That is, diameter: 6 inches, active layer N-type silicon, resistance value: 5 to 10 Ωcm, thickness: 10 μm,
Embedded oxide film thickness 1 μm, support substrate P type, resistance value 1
The thickness is 30 Ωcm and the thickness is 625 μm. The details of the mirror wafer are as follows. That is, diameter: 6 inches, N-type silicon, resistance value: 5 to 10 Ωcm, thickness: 625
μm. The details of the epitaxial wafer are as follows. That is, a resistance value of 6 inches is 1
A P-type epitaxial layer having a resistance value of 9.5 to 10.5 Ωcm is formed on a P-type mirror-finished silicon wafer having a resistance of 0 to 14 Ωcm.
μm was grown. The furnace used for the epitaxial growth is a single-wafer furnace with a load lock mechanism. The area of the gate oxide film is 1 × 10 ⁻² cm ² and the thickness is 25 nm. The non-defective rate indicates that the judgment current is 10
^-4 A, and the rate at which the gate oxide film was destroyed when a voltage of 8 MV / cm was applied was examined. This test is TZ
DB (Time Zero Dielectric B)
leakdown). As is clear from Table 1, when the copper concentration of the silicon wafer by the LTD method is 1.
Compared with Comparative Example 1, Comparative Example 2 and Comparative Example 3 exceeding 1 × 10 ¹¹ cm ⁻² , the copper concentration is 1.1 × 10 ¹¹ cm ^{−2.
-2 In} the wafers of the examples below, the yield rate of the oxide film withstand voltage was increased.

[0014]

According to the present invention, when a device is manufactured on the surface of a low copper concentration semiconductor wafer, the electrical characteristics of the device, particularly the withstand voltage of the oxide film, can be increased. As a result, the yield of device fabrication can be increased.

[Brief description of the drawings]

FIG. 1 is a flow sheet for explaining an LTD method according to an embodiment of the present invention.

FIG. 2 is a graph showing a recovery rate of copper by an LTD method according to one embodiment of the present invention.

Claims (4)

[Claims] 1. A low copper concentration semiconductor wafer having a copper concentration of 1.1 × 10 ¹¹ cm ⁻² or less when the semiconductor wafer is measured by an LTD method. 2. The low copper concentration semiconductor wafer according to claim 1, wherein the semiconductor wafer is a mirror-polished silicon wafer. 3. The low copper concentration semiconductor wafer according to claim 1, wherein the semiconductor wafer is an SOI wafer. 4. The low copper concentration semiconductor wafer according to claim 1, wherein said semiconductor wafer is an epitaxial wafer.