JPS6070839A - Clock extracting and switching system - Google Patents

Abstract

PURPOSE:To attain multiplex clock reception from duplicated clock reception by driving a counter with a clock oscillated from a clock interruption detecting circuit, using this counter output as a selector signal and attaining the connection to all clock reception circuits. CONSTITUTION:When the clock reception circuit 1 is failed, a clock reception fault signal 9 is outputted and also a clock signal 6 is interrupted, an output Q' of a clock interruption detecting circuit 3 goes to H, and a counter 5 is counted up by the oscillation block of an outgoing circuit 4. An output Q of the counter 5 becomes a selection signal of a selection circuit 2 to select one circuit of the circuit 1. When the circuit 1 is faulty, the counter 5 is counted up by the clock of the circuit 4, and the count is performed until the circuit is connected to the normal circuit 1, and when it is connected to the normal circuit 1, the output Q' of the circuit 3 goes to L, the oscillation of the circuit 4 is stopped and the counter 5 keeps the state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for detecting an abnormality in a receiving circuit and switching clock extraction to another receiving circuit.

[Background of the invention]

FIG. 1 is a circuit showing a conventional clock extraction switching method. In Figure 1, 1 is a clock receiving circuit, 2 is
6 is a selection circuit, and 6 is a state holding circuit.

Next, the operation shown in FIG. 1 will be explained.

Now assume that both the O and n circuits of 1 (clock receiving circuit) receive the clock normally. 5 (state holding circuit) is in the initial state Q-L by the initial setting signal 8. .In this state, 2 (switching circuit) is 0 of 1
Select the circuit and output the clock signal to 5. In this state, when a clock signal abnormality is detected in the 0 circuit of 1, the abnormality detection signal 7 becomes
The D input changes Q to H, and the 5 signals are fed to the clock from the 1 n circuit. Similarly, when n circuits are in a normal state, the output of 0 circuits is switched off and corrupted. In addition, when both the O and n receiving circuits of 1 are abnormal, the abnormality detection signals of both circuits are outputted to D7 as a reception abnormality signal to 6.

[Purpose of the invention]

An object of the present invention is to detect clock abnormalities from a clock receiver circuit at low cost using a simple circuit in a connection switching circuit between a number of clock receiving circuits and a circuit operated by a clock extracted from the receiving circuit. The purpose of this invention is to sequentially change the connections and extract the clock from those that are normally outputting the clock.

[Summary of the invention]

In order to achieve this object, the present invention provides a circuit that oscillates upon detection of a clock disconnection, uses the oscillation clock to run a counter, uses the counter output as a selector signal, and sequentially changes the connections so that all clocks can be It is located where it can be connected to the receiving circuit.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the present invention.

This will be explained below with reference to FIG. 1 is a clock receiving circuit, 2
6 is a selection circuit, 6 is a clock cutoff adjustment circuit, 4 is an oscillation circuit,
5 is a counter, 6 is a clock signal, 7 is a selected clock signal, 8 is a clock reception abnormal signal, and 9 is a clock reception abnormal signal. Assume that a signal is being output. Here, if 1 becomes abnormal, 9 is output and the signal B is disconnected, and the disconnection is detected by 6. When the disconnection is detected by 3, the output Q of 5 becomes H and 4 oscillates, and 5 counts up by the oscillation clock. The Q output of 5 becomes a selection signal of 2, which selects between circuit 1 and circuit 1. If the clock receiving circuit is abnormal, 5 oscillation clocks are added to the 4 oscillation clocks.
counts up and is similarly selected as 2 circuits of 1.

The above operation 1' continues until the normal clock receiving circuit is connected by repeating the above, and when it is connected to the normal clock receiving circuit, the clock is detected by 6 ◇ = L and 4
oscillation stops and 5 maintains its state. As a result, 2 continues to be connected to the normal clock receiving circuit 126 times. Similarly, if one of the trial main clock receiving circuits becomes abnormal, it is switched to the next receiving circuit and the switching continues until there is a normal receiving circuit. If all 1's are abnormal, a signal is output to 8 and the clock becomes abnormal.

〔Effect of the invention〕

By utilizing the present invention, it is possible to realize from duplex clock reception to multiplex clock reception with a simple circuit at low cost, and there is an effect that high reliability can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional clock reception switching method, and FIG. 2 is a circuit diagram of a clock extraction switching method according to an embodiment of the present invention. 1... Clock receiving circuit, 2... Selection circuit, 4...
・Oscillation circuit, 5...Counter. Cultivation / Diagram No. 2

Claims (1)

[Claims] 11. In a circuit that switches connections between multiple clock receiving circuits and a circuit operated by a clock extracted from the receiving circuit, detects a clock abnormality in the connected receiving circuit, sequentially changes the connection, and automatically connects to a normal receiving circuit. This clock extraction switching method is characterized by: