JPS6070741A - Interelement isolation - Google Patents

Abstract

PURPOSE:To improve an electrically insulating property between elements, to enable to form the pattern of a buried insulating layer in a minute shape, and to contrive to enhance the degree of integration of the elements by a method wherein a groove is formed at the part to separate between the elements on the main surface part of a semiconductor substrate, and an insulator is buried in the groove thereof to form an insulating layer. CONSTITUTION:A groove 15 is formed selectively according to the anisotropic etching method to the part to separate between the first element forming region 2 and the second element forming region 3 of the main surface part of a p type silicon substrate 1. An insulator is deposited according to the bias sputtering method on the main surface containing the groove 15 of the p type silicon substrate 1 to form an insulating layer 16. The surface of the insulating layer 16 is flattened according to the bias sputtering method thereof, and no cavity is generated to the part inside of the groove 15 of the insulating layer 16. The insulating layer 16 is etched finally to remove the part excluding the part inside of the groove 15 of the insulating layer 16, and the part left in the groove 15 of the insulating layer 16 is made to a buried insulating layer 16a for isolation between the elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for isolating elements in the manufacturing process of large-scale semiconductor integrated circuit devices (LSI) and the like.

[Prior art]

FIG. 1 is a cross-sectional view for explaining an example of a conventional isolation method between elements using a pn junction.

This conventional method involves forming a first element formation region (2) and a second element formation region (3) on the main surface of a p-type silicon substrate (1).
) to form an n-type separation diffusion layer (4) by selectively diffusing n-type impurities into the portion to be separated from the n-type separation diffusion layer (4).
4) and the p-type silicon substrate (1).
Due to the junction (, r), the element formation area +21, +3
This is to electrically isolate between.

However, in this conventional method, the capacitance of the pn junction (J), the element formation region (21, (31) and the n-type isolation diffusion layer (4)
), and the width of the pattern of the n-type isolation diffusion layer (4) is several microns.
Since the number of pixels is about m, there is a problem in terms of the degree of integration of the elements.

FIG. 2 is a cross-sectional view for explaining an example of a conventional isolation method between elements by embedding an insulator.

This conventional method involves forming a first element formation region (2) and a second element formation region (3) on the main surface of a p-type silicon substrate (1).
A trench (5) is selectively formed in the part to be separated from the device by wet etching, and an insulator formed by the CVD method is buried in the trench (5) to form a buried insulating layer ( 6).

In this conventional method, the elements are separated by the buried insulating layer (6), so there is no electrical influence due to junction capacitance or parasitic transistors as in the conventional example shown in FIG.
Good electrical insulation between elements.

However, since the side wall surface of the groove (5) expands upward by G due to side etching when forming the groove (6), it is not possible to embed the insulator in the groove (5) so that the surface is flat. , there is a problem that unevenness is formed on the surface of the buried insulator N(6). As the sidewall surface of the trench (5) expands upward in the case, the pattern width of the buried insulating layer (6) increases, making it impossible to solve the problem of device integration.

FIG. 3 is a cross-sectional view illustrating another example of the conventional isolation method between elements by embedding an insulator.

This conventional method involves forming a first element formation region (2) and a second element formation region (3) on the cut surface of a p-type silicon substrate (1).
) and selectively insert grooves (5a) in the areas where they should be separated.

It is formed by a directional etching method, and an insulating material formed by a sputtering method is buried in the groove (5a) to form a buried insulating layer (6a) for isolation between elements.

In this conventional method, the electrical insulation between elements is as good as in the conventional example shown in FIG.
) is hardly expanded upward, the pattern width of the buried insulating layer (6a) is reduced, and problems in terms of device integration can be solved. However, since the insulator formed by sputtering cannot be completely buried in the groove (5a), the buried insulating layer (6a)
) is uneven on the surface, and the buried insulation N (6a
) There is a problem in that a cavity as illustrated by the symbol A in the figure is formed inside.

[Summary of the invention]

This invention has been made to solve the above-mentioned problems.A groove is formed in the main surface of a semiconductor substrate at a portion where the elements are to be separated by an anisotropic etching method. By embedding an insulator formed of oxide to form a buried insulating layer for isolation between elements, electrical insulation between elements is good, the pattern of the buried insulating layer can be made finer, and the pattern of the buried insulating layer can be made finer. The present invention provides a device isolation method with a flat surface.

[Embodiments of the invention]

FIGS. 4A to 4C are cross-sectional views showing the main stages of a device isolation method according to an embodiment of the present invention by embedding an insulator.

First, as shown in FIG. 4(A), a first element formation region (2) and a second element formation region (3) are formed on the cut surface of a p-type silicon substrate (fl), which is a semiconductor substrate in this example. ) and 06) are selectively formed in the portions to be separated using an anisotropic etching method. Next, as shown in Figure 2 (B), an insulating layer (16) is formed by depositing an insulator on the main surface of the p-type silicon substrate (1), including the inside of the groove θ5), by bias sputtering. do. In this bias sputtering method, for example, the insulator is sputtered onto a p-type silicon substrate by sputtering most of the Ar ions generated by activating low-pressure argon (Ar) gas.
The insulating layer (1
6), the surface of the insulating layer (16) becomes flat, and a cavity (a) as illustrated in FIG. 3 is not formed in the portion of the insulating layer 06) inside the groove (15).

Finally, the insulating layer 06) is etched to form the insulating layer 06).
) of the groove 05) is removed, and the insulating layer (l
The work of the method of this embodiment is completed when the portion left in the groove (15) of (il) is made into a buried insulator/1l (16a) for isolation between elements.

In the method of this example, the surface of the insulating layer (16) formed by bias sputtering is flat, and the surface of the insulating layer (16) is flat.
Since a cavity is not formed in the groove 06) of 6), the buried insulating layer obtained by etching this insulating layer θ6) is
The surface of 16a) is also flat and there are no cavities inside. Furthermore, since the elements are separated by the buried insulating layer (16a), the electrical insulation between the elements is good, similar to the conventional example shown in FIG. Furthermore, since there is almost no side etching in the anisotropic etching method, the pattern width of the buried insulating layer (16a) can be reduced and the degree of integration of the device can be improved, similar to the conventional example shown in FIG. I can do it.

In this example, a p-type silicon substrate (1) was used, but
This does not necessarily have to be a p-type silicon substrate, but an n
It may be a shaped silicon substrate, or it may be a semiconductor substrate other than a silicon substrate.

〔Effect of the invention〕

As explained above, in the device isolation method of the present invention, grooves are formed by anisotropic etching in the portions of the main surface of the semiconductor substrate where the devices are to be separated. After forming an insulating layer by depositing an insulating material on the surface using a bias sputtering method, this insulating layer is etched to remove the portions of the insulating layer other than the portions within the grooves, leaving only the portions of the insulating layer in the grooves. Since the buried portion is used as a buried insulating layer for element isolation, the surface of the insulating layer formed by bias sputtering is flat, and no cavities are formed in the grooves of the insulating layer. Therefore, the surface of the buried insulating layer obtained by etching this insulating layer is also flat, and there is no cavity inside. Since the elements are separated by a buried insulating layer, the electrical insulation between the elements is good. On the other hand, since there is almost no side etching in anisotropic etching, the backing width of the buried insulating layer is reduced, and the degree of integration of the confectionery can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining an example of a conventional isolation method between elements using a pn junction, and FIGS.
fil is a p-type silicon substrate (semiconductor base ti), (1
5) is a groove, tie) is an insulating layer, and (16a) is a buried insulating layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) 1. Indication of case: Japanese Patent Application No. 58-l MA9646 No. 2, title of invention: Element separation method 3, person making amendment Relationship with case Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name:
(601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Claims column 6 of the agent's specification, Contents of amendment (1) The claims of the specification are corrected as shown in the attached appendix. 7. Documents showing the scope of claims after the list of attached documents has been corrected One or more copies Claims (1) Grooves are formed by anisotropic etching in the portion of the main surface of the semiconductor substrate where the elements are to be separated. a step of depositing an insulating material by bias sputtering on the main surface of the semiconductor substrate including the inside of the groove to form an insulating layer; and etching the insulating layer to form a portion of the insulating layer inside the groove. An inter-element isolation method comprising the step of removing the remaining portion of the insulating layer and using the portion left in the groove of the insulating layer as a buried insulating layer for inter-element isolation.

Claims (1)

[Claims] (1) A step of forming a groove by an anisotropic etching method in a part of the main surface of the semiconductor substrate where the elements are to be separated; a step of depositing and forming an insulating layer; etching the insulating layer to remove a portion of the insulating layer other than the portion within the groove; and a portion of the insulating layer remaining within the groove for isolation between elements; An inter-element isolation method comprising a step of forming a buried insulating layer.